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參數(shù)資料
| 型號： | AK4393 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | ADVANCED MULTI-BIT 96KHZ 24-BIT DAC |
| 中文描述： | 先進(jìn)的多位96kHz的24位DAC |
| 文件頁數(shù)： | 7/22頁 |
| 文件大小： | 235K |
| 代理商： | AK4393 |
ASAHI KASEI
[AK4393]
M0039-E-01
2000/5
- 7 -
SWITCHING CHARACTERISTICS
(Ta = 25
°
C; AVDD = 4.75~5.25V; DVDD = 3.0~5.25V; C
L
= 20pF)
Parameter
Master Clock Timing
Normal Speed: 256fs, Double Speed: 128fs
Pulse Width Low
Pulse Width High
Normal Speed: 384fs, Double Speed: 192fs
Pulse Width Low
Pulse Width High
Normal Speed: 512fs, Double Speed: 256fs
Normal Speed: 768fs, Double Speed: 384fs
Pulse Width Low
Pulse Width High
LRCK Frequency
(Note 17)
Normal Speed Mode (DFS = “L”)
Double Speed Mode (DFS = “H”)
Duty Cycle
Serial Interface Timing
BICK Period
BICK Pulse Width Low
Pulse Width High
BICK “
-
” to LRCK Edge (Note 18)
LRCK Edge to BICK “
-
” (Note 18)
SDATA Hold Time
SDATA Setup Time
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN High Time
CSN “
ˉ
” to CCLK “
-
”
CCLK “
-
” to CSN “
-
”
Reset Timing
PDN Pulse Width (Note 19)
Symbol
min
typ
max
Units
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fCLK
fCLK
tCLKL
tCLKH
7.7
28
28
11.5
20
20
15.4
23.0
7
7
13.824
MHz
ns
ns
MHz
ns
ns
MHz
MHz
ns
ns
20.736
27.648
41.472
fsn
fsd
Duty
30
60
45
44.1
88.2
54
108
55
kHz
kHz
%
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
140
60
60
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
200
80
80
50
50
150
50
50
ns
ns
ns
ns
ns
ns
ns
ns
tPW
150
ns
Notes: 17. When the normal and double speed modes are switched, AK4393 should be reset by PDN pin or RSTN bit.
18. BICK rising edge must not occur at the same time as LRCK edge.
19. The AK4393 can be reset by bringing PDN “L” to “H”.
When the states of CKS2-0 or DFS change, the AK4393 should be reset by PDN pin or RSTN bit.
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