- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385091 > AK4388ET (Asahi Kasei Microsystems Co.,Ltd) 192kHz 24-Bit 2ch ツヒ DAC PDF資料下載
參數(shù)資料
| 型號： | AK4388ET |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 192kHz 24-Bit 2ch ツヒ DAC |
| 中文描述： | 192kHz的24位2通道ツヒ數(shù)模轉(zhuǎn)換器 |
| 文件頁數(shù)： | 8/18頁 |
| 文件大?。?/td> | 198K |
| 代理商： | AK4388ET |
ASAHI KASEI
[AK4388]
MS0485-E-01
2006/07
- 8 -
OPERATION OVERVIEW
System Clock
The external clocks, which are required to operate the AK4388, are MCLK, LRCK and BICK. The master clock (MCLK)
should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation
filter and the delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS
pin = “L”, Normal Speed Mode), the frequency of MCLK is set automatically (Table 1). After exiting reset (RSTN pin=
“
↑
”), the AK4388 is in Auto Setting Mode. In Auto Setting Mode (ACKS pin = “H”), as MCLK frequency is detected
automatically (Table 2), and the internal master clock becomes the appropriate frequency (Table 3).
All external clocks (MCLK,BICK and LRCK) should always be present whenever the AK4388 is in the normal operation
mode (RSTN pin = ”H”). If these clocks are not provided, the AK4388 may draw excess current and may fall into
unpredictable operation. This is because the device utilizes dynamic refreshed logic internally. The AK4388 should be
reset by RSTN pin = “L” after threse clocks are provided. If the external clocks are not present, the AK4388 should be in
the power-down mode (RSTN pin = “L”). After exiting reset at power-up etc., the AK4388 is in the power-down mode
until MCLK and LRCK are input.
LRCK
MCLK
fs
256fs
384fs
512fs
32.0kHz
8.1920MHz 12.2880MHz
16.3840MHz
44.1kHz
11.2896MHz 16.9344MHz
22.5792MHz
48.0kHz
12.2880MHz 18.4320MHz
24.5760MHz
BICK
64fs
2.0480MHz
2.8224MHz
3.0720MHz
768fs
1152fs
36.8640MHz
N/A
N/A
24.5760MHz
33.8688MHz
36.8640MHz
Table 1. System Clock Example (Manual Setting Mode, ACKS pin = “L”, Normal Speed Mode)
Mode
Normal
Normal
Double
Quad
MCLK
1152fs
Sampling Rate
8kHz~32kHz
8kHz~48kHz
32kHz~96kHz
120kHz~192kHz
512fs
256fs
128fs
768fs
384fs
192fs
Table 2. Sampling Speed (Auto Setting Mode, ACKS pin = “H”)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
MCLK (MHz)
384fs
12.2880
16.9344
18.4320
33.8688
36.8640
-
-
128fs
-
-
-
-
-
22.5792
24.5760
192fs
-
-
-
-
-
33.8688
36.8640
256fs
8.1920
11.2896
12.2880
22.5792
24.5760
-
-
512fs
16.3840
22.5792
24.5760
-
-
-
-
768fs
24.5760
33.8688
36.8640
-
-
-
-
1152fs
36.8640
-
-
-
-
-
-
Table 3. System Clock Example (Auto Setting Mode, ACKS pin = “H”)
When MCLK= 256fs/384fs, the Auto Setting Mode supports sampling rate of 32kHz~96kHz (Table 2). But, when the
sampling rate is 32kHz~48kHz, DR and S/N will degrade by approximately 3dB as compared to when MCLK=
512fs/768fs.
ACKS pin
MCLK
L
256fs/384fs/512fs/768fs
H
256fs/384fs
H
512fs/768fs
DR,S/N
106dB
103dB
106dB
Table 4. Relationship between MCLK frequency and DR, S/N (fs= 44.1kHz)
相關PDF資料 |
PDF描述 |
|---|---|
| AK4388VT | 192kHz 24-Bit 2ch ツヒ DAC |
| AK4393VF | ADVANCED MULTI-BIT 96KHZ 24-BIT DAC |
| AK4393 | ADVANCED MULTI-BIT 96KHZ 24-BIT DAC |
| AK4394 | ADVANCED MULTI-BIT 192KHZ 24-BIT DAC |
| AK4394VF | ADVANCED MULTI-BIT 192KHZ 24-BIT DAC |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AK4388ETP-E2 | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述: |
| AK4388VT | 制造商:AKM 制造商全稱:AKM 功能描述:192kHz 24-Bit 2ch ツヒ DAC |
| AK4390 | 制造商:AKM 制造商全稱:AKM 功能描述:Ultra Low Latency 32-Bit ΔΣ DAC |
| AK4390EF | 制造商:AKM 制造商全稱:AKM 功能描述:Ultra Low Latency 32-Bit ΔΣ DAC |
| AK4390EFP-E2 | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。