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參數(shù)資料
| 型號： | AK4388ET |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 192kHz 24-Bit 2ch ツヒ DAC |
| 中文描述： | 192kHz的24位2通道ツヒ數(shù)模轉(zhuǎn)換器 |
| 文件頁數(shù)： | 12/18頁 |
| 文件大?。?/td> | 198K |
| 代理商： | AK4388ET |
ASAHI KASEI
[AK4388]
MS0485-E-01
2006/07
- 12 -
System Reset
The AK4388 must be reset once by bringing RSTN pin = “L” upon power-up. The AK4388 is powered up and the internal
timing starts clocking by LRCK “
↑
” after exiting reset and power down state by MCLK. The AK4388 is in the
power-down mode until LRCK are input.
Power ON/OFF timing
AK4388 is placed in the power-down mode by bringing RSTN pin “L” and the registers are initialized. The analog
outputs go to VCOM (VDD/2). Since some click noise occurs at the edge of the RSTN signal, the analog output should
be muted externally if the click noise influences system application.
RSTN pin
Power
Reset
Normal Operation
Clock In
MCLK,LRCK,BICK
DAC In
(Digital)
DAC Out
(Analog)
External
Mute
Mute ON
(5)
DZF
Don’t care
“0”data
GD
(1)
(3)
(4)
(6)
GD
(3)
Mute ON
“0”data
Don’t care
Internal
State
(2)
(2)
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs are VCOM (VDD/2) in power-down mode.
(3) Click noise occurs at the edge of RSTN signal. This noise is output even if “0” data is input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (RSTN pin = “L”).
(5) Mute the analog output externally if the click noise (3) influences the system application.
The timing example is shown in this figure.
(6) DZF pins are “L” in the power-down mode (RSTB pin = “L”).
Figure 6. Power-down/up Sequence Example
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