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參數(shù)資料
| 型號： | AK4385VT |
| 廠商： | ASAHI KASEI POWER DEVICES CORP |
| 元件分類： | DAC |
| 英文描述： | 108dB 192kHz 24-Bit 2ch ツヒ DAC |
| 中文描述： | SERIAL INPUT LOADING, 24-BIT DAC, PDSO16 |
| 封裝： | 6.40 X 5 MM, 0.65 MM PITCH, LEAD FREE, PLASTIC, TSSOP-16 |
| 文件頁數(shù)： | 9/21頁 |
| 文件大小： | 285K |
| 代理商： | AK4385VT |
ASAHI KASEI
[AK4385]
MS0246-E-00
2003/07
- 9 -
OPERATION OVERVIEW
System Clock
The external clocks, which are required to operate the AK4385, are MCLK, LRCK and BICK. The master clock (MCLK)
should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation
filter and the delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS =
“0”: Register 00H), the sampling speed is set by DFS0/1(Table 1). The frequency of MCLK at each sampling speed is set
automatically. (Table 2~4).After exiting reset (PDN = “
↑
”), the AK4385 is in Auto Setting Mode. In Auto Setting Mode
(ACKS = “1”: Default), as MCLK frequency is detected automatically (Table 5), and the internal master clock becomes
the appropriate frequency (Table 6), it is not necessary to set DFS0/1.
All external clocks (MCLK,BICK and LRCK) should always be present whenever the AK4385 is in the normal operation
mode (PDN= ”H”). If these clocks are not provided, the AK4385 may draw excess current and may fall into unpredictable
operation. This is because the device utilizes dynamic refreshed logic internally. The AK4385 should be reset by PDN=
“L” after threse clocks are provided. If the external clocks are not present, the AK4385 should be in the power-down
mode (PDN= “L”). After exiting reset at power-up etc., the AK4385 is in the power-down mode until MCLK and LRCK
are input.
DFS1
DFS0
0
0
Normal Speed Mode
0
1
Double Speed Mode
1
0
Quad Speed Mode
Table 1. Sampling Speed (Manual Setting Mode)
LRCK
MCLK
fs
256fs
384fs
512fs
32.0kHz
8.1920MHz 12.2880MHz
16.3840MHz
44.1kHz
11.2896MHz 16.9344MHz
22.5792MHz
48.0kHz
12.2880MHz 18.4320MHz
24.5760MHz
Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode)
LRCK
MCLK
fs
128fs
192fs
88.2kHz
11.2896MHz 16.9344MHz
22.5792MHz
96.0kHz
12.2880MHz 18.4320MHz
24.5760MHz
Table 3. System Clock Example (Double Speed Mode @Manual Setting Mode)
LRCK
MCLK
fs
128fs
176.4kHz
22.5792MHz
33.8688MHz
192.0kHz
24.5760MHz
36.8640MHz
Table 4. System Clock Example (Quad Speed Mode @Manual Setting Mode)
Sampling Rate (fs)
8kHz~48kHz
60kHz~96kHz
120kHz~192kHz
Default
BICK
64fs
2.0480MHz
2.8224MHz
3.0720MHz
768fs
1152fs
36.8640MHz
N/A
N/A
24.5760MHz
33.8688MHz
36.8640MHz
BICK
64fs
5.6448MHz
6.1440MHz
256fs
384fs
33.8688MHz
36.8640MHz
BICK
64fs
192fs
11.2896MHz
12.2880MHz
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4385VTP-E2 | 制造商:AKM Semiconductor Inc 功能描述:AK4385VTP-E2 |
| AK4386 | 制造商:AKM 制造商全稱:AKM 功能描述:100DB 96KHZ 24 BIT 2CH |
| AK4386ET | 制造商:AKM 制造商全稱:AKM 功能描述:100dB 96kHz 24-Bit 2ch ???￡ DAC |
| AK4386ETP-E2 | 功能描述:IC DAC 24BIT STEREO 16TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 設(shè)置時間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
| AK4386VT | 制造商:AKM 制造商全稱:AKM 功能描述:100DB 96KHZ 24 BIT 2CH |
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