參數(shù)資料
型號: AK4385VT
廠商: ASAHI KASEI POWER DEVICES CORP
元件分類: DAC
英文描述: 108dB 192kHz 24-Bit 2ch ツヒ DAC
中文描述: SERIAL INPUT LOADING, 24-BIT DAC, PDSO16
封裝: 6.40 X 5 MM, 0.65 MM PITCH, LEAD FREE, PLASTIC, TSSOP-16
文件頁數(shù): 13/21頁
文件大?。?/td> 285K
代理商: AK4385VT
ASAHI KASEI
[AK4385]
MS0246-E-00
2003/07
- 13 -
Zero Detection
The AK4385 has channel-independent zeros detect function. When the input data at each channel is continuously zeros
for 8192 LRCK cycles, DZF pin of each channel goes to “H”. DZF pin of each channel immediately goes to “L” if input
data of each channel is not zero after going DZF “H”. If RSTN bit is “0”, DZF pins of both channels go to “H”. DZF pin
of both channels go to “L” at 2~3/fs after RSTN bit returns to “1”. If DZFM bit is set to “1”, DZF pins of both channels go
to “H” only when the input data at both channels are continuously zeros for 8192 LRCK cycles. Zero detect function can
be disabled by DZFE bit. In this case, DZF pins of both channels are always “L”. DZFB bit can invert the polarity of DZF
pin.
Soft Mute Operation
Soft mute operation is performed at digital domain. When the SMUTE bit goes to “1”, the output signal is attenuated by
-
during ATT_DATA
×
ATT transition time (Table 9) from the current ATT level. When the SMUTE bit is returned to
“0”, the mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATA
×
ATT
transition time. If the soft mute is cancelled before attenuating to -
after starting the operation, the attenuation is
discontinued and returned to ATT level by the same cycle. The soft mute is effective for changing the signal source
without stopping the signal transmission.
SMUTE bit
Attenuation
DZF pin
ATT Level
-
AOUT
8192/fs
GD
(2)
GD
(1)
(3)
(4)
(1)
Notes:
(1) ATT_DATA
×
ATT transition time (Table 9). For example, in Normal Speed Mode, this time is 1020LRCK cycles
(1020/fs) at ATT_DATA=255.
(2) The analog output corresponding to the digital input has a group delay, GD.
(3) If the soft mute is cancelled before attenuating to -
after starting the operation, the attenuation is discontinued and
returned to ATT level by the same cycle.
(4) When the input data at each channel is continuously zeros for 8192 LRCK cycles, DZF pin of each channel goes to
“H”. DZF pin immediately goes to “L” if input data are not zero after going DZF “H”.
Figure 5. Soft Mute and Zero Detection
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