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參數(shù)資料
| 型號： | AK4382VT |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 112dB 192kHz 24-BIT SCH DAC |
| 中文描述： | 一一二分貝192kHz的24位三星援 |
| 文件頁數(shù)： | 18/21頁 |
| 文件大?。?/td> | 251K |
| 代理商： | AK4382VT |
ASAHI KASEI
[AK4382]
MS0034-E-00
2000/7
- 18 -
DZFM: Data Zero Detect Mode
0: Channel Separated Mode
1: Channel ANDed Mode
If the DZFM bit is set to “1”, the DZF pins of both channels go to “H” only when the input data at both
channels are continuously zeros for 8192 LRCK cycles.
Addr
02H
Register Name
Control 3
default
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
0
0
D2
D1
0
0
D0
0
0
DZFB
0
DZFB: Inverting Enable of DZF
0: DZF goes “H” at Zero Detection
1: DZF goes “L” at Zero Detection
Addr
03H
04H
Register Name
Lch ATT
Rch ATT
default
D7
D6
D5
D4
D3
D2
D1
D0
ATT7
ATT7
1
ATT6
ATT6
1
ATT5
ATT5
1
ATT4
ATT4
1
ATT3
ATT3
1
ATT2
ATT2
1
ATT1
ATT1
1
ATT0
ATT0
1
ATT = 20 log (ATT_DATA / 255) [dB]
00H: Mute
SYSTEM DESIGN
Figure 9 shows the system connection diagram. An evaluation board (AKD4382) is available in order to allow an easy
study on the layout of a surrounding circuit.
MCLK
1
BICK
2
SDTI
3
LRCK
4
PDN
5
CSN
6
CCLK
7
CDTI
8
DZFL
16
DZFR
15
VDD
14
VSS
13
AOUTL+
12
AOUTL-
11
AOUTR+
10
AOUTR-
9
Master Clock
Micro-
controller
AK4382
fs
24bit Audio Data
Reset & Power down
64fs
10u
0.1u
+
Lch
LPF
Rch
LPF
Rch Out
Lch Out
Analog Ground
Digital Ground
Lch
MUTE
Rch
MUTE
Analog
Supply 5V
Figure 9. Typical Connection Diagram
Notes:
- LRCK = fs, BICK = 64fs.
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive
load.
- All input pins except pull-down/pull-up pins should not be left floating.
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