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參數(shù)資料
| 型號(hào)： | AK4360 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | Low Power 2ch ΔΣ DAC with HP-AMP(帶耳機(jī)放大器的20位低電壓低功耗立體聲D/A轉(zhuǎn)換器) |
| 中文描述： | 低功耗2通道ΔΣDAC，帶有惠普腺苷（帶耳機(jī)放大器的20位低電壓低功耗立體聲的D / A轉(zhuǎn)換器） |
| 文件頁(yè)數(shù)： | 9/16頁(yè) |
| 文件大?。?/td> | 81K |
| 代理商： | AK4360 |
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ASAHI KASEI
[AK4360]
MS0072-E-00
2001/01
- 9 -
OPERATION OVERVIEW
n
System Clock
The external clocks that are required to operate the AK4360 are MCLK (256fs/384fs), LRCK (fs) and BICK (32fs
～
). The
master clock (MCLK) should be synchronized with LRCK but the phase is not critical. The frequency of MCLK is
determined by the sampling rate (LRCK) and CKS pin. Setting CKS = “L” selects an MCLK frequency of 256fs while
setting CKS = “H” selects 384fs. When the 384fs is selected, the internal master clock becomes 256fs(=384fs*2/3). Table
1 illustrates standard audio word rates and corresponding frequencies used in the AK4360.
All external clocks (MCLK, BICK, LRCK) should always be present whenever the AK4360 is in normal operation mode
(PDN = “H”). If these clocks are not provided, the AK4360 may draw excess current because the device utilizes dynamic
refreshed logic internally. If the external clocks are not present, the AK4360 should be in the power-down mode(PDN =
“L”).
MCLK
LRCK (fs)
CKS = “L”: 256fs
8.1920MHz
11.2896MHz
12.2880MHz
Table 1. Examples of System Clock
CKS = “H”: 384fs
12.2880MHz
16.9344MHz
18.4320MHz
BICK (64fs)
32.0kHz
44.1kHz
48.0kHz
2.0480MHz
2.8224MHz
3.0720MHz
MCLK
CKS
256fs or 384fs
H
L
256fs
2/3
Figure 4. MCLK Divider Circuit
n
Audio Interface Format
The AK4360 interfaces with external system by using SDATA, BICK and LRCK pins. Two types of data format are
available and one of them is selected by setting DIF pin. In mode 1, if BICK
≥
40fs, 16bit data followed by four zeros also
could be input, 18bit data followed by two zeros also could be input. In all modes, the serial data is MSB first and 2’s
complement format.
DIF pin
L
Mode
BICK
≥
32fs
≥
32fs
≥
36fs
≥
40fs
Figure
Figure 5
0: 16bit LSB Justified
1: 16bit, I
2
S Compatible
1: 18bit, I
2
S Compatible
1: 20bit, I
2
S Compatible
H
Figure 6
Table 2. Audio Formats
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK4363 | 96KHz 24 Bit ΔΣ DAC with PLL(帶鎖相環(huán)的采樣速度96KHz，24位立體聲 ΔΣ D/A轉(zhuǎn)換器) |
| AK4363VF | 96kHz 24Bit DAC with PLL |
| AK4364 | 96kHz 24BIT DAC WITH PLL AND DIT |
| AK4364VF | 96kHz 24BIT DAC WITH PLL AND DIT |
| AK4365VN | DAC with built-in PLL & HP-AMP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4361024D | 制造商:ACCUTEK 制造商全稱:ACCUTEK MICROCIRCUIT CORPORATION 功能描述:65,536 x 32 Bit CMOS/BiCMOS Static Random Access Memory |
| AK4361024G | 制造商:ACCUTEK 制造商全稱:ACCUTEK MICROCIRCUIT CORPORATION 功能描述:65,536 x 32 Bit CMOS/BiCMOS Static Random Access Memory |
| AK4361024S | 制造商:ACCUTEK 制造商全稱:ACCUTEK MICROCIRCUIT CORPORATION 功能描述:65,536 x 32 Bit CMOS/BiCMOS Static Random Access Memory |
| AK4361024W | 制造商:ACCUTEK 制造商全稱:ACCUTEK MICROCIRCUIT CORPORATION 功能描述:65,536 x 32 Bit CMOS/BiCMOS Static Random Access Memory |
| AK4361024Z | 制造商:ACCUTEK 制造商全稱:ACCUTEK MICROCIRCUIT CORPORATION 功能描述:32,768 x 32 Bit CMOS / BiCMOS Static Random Access Memory |
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