參數(shù)資料
型號: AK4360
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: Low Power 2ch ΔΣ DAC with HP-AMP(帶耳機放大器的20位低電壓低功耗立體聲D/A轉(zhuǎn)換器)
中文描述: 低功耗2通道ΔΣDAC,帶有惠普腺苷(帶耳機放大器的20位低電壓低功耗立體聲的D / A轉(zhuǎn)換器)
文件頁數(shù): 14/16頁
文件大?。?/td> 81K
代理商: AK4360
ASAHI KASEI
[AK4360]
MS0072-E-00
2001/01
- 14 -
SYSTEM DESIGN
Figure 9
shows the system connection diagram. An evaluation board [AKD4360] is available in order to allow an easy study
on the layout of a surrounding circuit.
External
Clock
Reset
Audio
Data
Processor
1 MCLK
2 PDN
3 BICK
4 SDATA
5 LRCK
6 MT0
7 MT1
8 DEM
9 MUTEN
10 BOOST
11 CKS
12 DIF
Mode
Setting
Mute
Control
AK4360
TST1 24
TST2 23
VDD 22
VSS 21
VREF 20
VCOM 19
TST3 18
HPVCC 17
HPGND 16
NC 15
AOUTL 14
AOUTR 13
0.1
μ
10
μ
1
μ
0.1
μ
1
μ
0.1
μ
Analog
1.8 ~ 3.3V
0.1
μ
10
μ
Analog
0.9 ~ 3.3V
0.22
μ
0.22
μ
10
10
220
μ
220
μ
16
16
Headphone
Figure 9. Typical Connection Diagram
Notes:
- LRCK = fs, BICK
32fs, MCLK = 256fs/384fs.
- All input pins except NC and pull-down pins should not be left floating.
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive
load.
- Digital signals, especially clocks, should be kept away from the VREF and VCOM pins in order to avoid unwanted
coupling the AK4360.
1. Grounding and Power Supply Decoupling
VDD and VSS are supplied from analog supply and should be separated from system digital supply. Decoupling capacitor
for high frequency should be placed as near to VDD as possible.
2. Voltage Reference
The voltage reference is output on the VREF pin. An electrolytic capacitor 1.0
μ
F parallel with a 0.1
μ
F ceramic capacitor
are attached between VREF and VSS pins. Especially, the ceramic capacitor should be connected to VREF pin as near as
possible. No load current may be taken from the VREF output pin. All signals, especially clocks, should be kept away from
the VREF pin in order to avoid unwanted coupling into the AK4360.
3. Analog Outputs
The analog outputs are single-ended and centered around the VCOM voltage. The output signal range is typically 1.0Vpp.
The output voltage is a positive full scale for 7FFFH(@16bit) and a negative full scale for 8000H(@16bit). The ideal
output is VCOM voltage (typ: 0.48V) for 0000H(@16bit).
相關PDF資料
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