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參數(shù)資料
| 型號： | AK4358VQ |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 192 KHZ 24 BIT 8 CH DAC WITH DSD INPUT |
| 中文描述： | 192千赫24位8路DAC，具有DSD輸入 |
| 文件頁數(shù)： | 13/35頁 |
| 文件大小： | 457K |
| 代理商： | AK4358VQ |
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ASAHI KASEI
[AK4358]
MS0203-E-00
2003/02
- 13 -
OPERATION OVERVIEW
D/A Conversion Mode
The AK4358 can perform D/A conversion for both PCM data and DSD data. When DSD mode, DSD data can be input
from DCLK, DSDL1-4 and DSDR1-4 pins. When PCM mode, PCM data can be input from BICK, SDTI1-4 and LRCK
pins. PCM/DSD mode changes by D/P bit. When PCM/DSD mode changes by D/P bit, the AK4358 should be reset by
RSTN bit, PW bit (PW1=PW2=PW3=PW4= “0”) or PDN pin. It takes about 2/fs to 3/fs to change the mode.
D/P bit
DAC Output
0
PCM
1
DSD
Table 1. DSD/PCM Mode Control
System Clock
1) PCM Mode
The external clocks, which are required to operate the AK4358, are MCLK, LRCK and BICK. The master clock (MCLK)
should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation
filter and the delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS =
“0”: Register 00H), the sampling speed is set by DFS0/1(Table 2). The frequency of MCLK at each sampling speed is set
automatically. (Table 3~Table 5). In Auto Setting Mode (ACKS = “1”: Default), as MCLK frequency is detected
automatically (Table 6), and the internal master clock becomes the appropriate frequency (Table 7), it is not necessary to
set DFS0/1. When ACKSN = “H”, regardless of ACKS bit setting the AK4358 operates by Manual Setting Mode. When
ACKSN = “L”, ACKS bit setting is valid.
All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4358 is in the normal operation
mode (PDN= ”H”). If these clocks are not provided, the AK4358 may draw excess current and may fall into unpredictable
operation. This is because the device utilizes dynamic refreshed logic internally. The AK4358 should be reset by PDN =
“L” after threse clocks are provided. If the external clocks are not present, the AK4358 should be in the power-down
mode (PDN= ”L”). After exiting reset(PDN = “
↑
”) at power-up etc., the AK4358 is in the power-down mode until MCLK
is input. DSD interface signals (DCLK, DSDL1-4, DSDR1-4) are fixed to “H” or “L”.
DFS1
DFS0
0
0
Normal Speed Mode
0
1
Double Speed Mode
1
0
Quad Speed Mode
Sampling Rate (fs)
8kHz~48kHz
60kHz~96kHz
120kHz~192kHz
Default
Table 2. Sampling Speed (Manual Setting Mode)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
MCLK
BICK
64fs
2.0480MHz
2.8224MHz
3.0720MHz
256fs
384fs
512fs
768fs
8.1920MHz 12.2880MHz
11.2896MHz 16.9344MHz
12.2880MHz 18.4320MHz
16.3840MHz
22.5792MHz
24.5760MHz
24.5760MHz
33.8688MHz
36.8640MHz
Table 3. System Clock Example (Normal Speed Mode @Manual Setting Mode)
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相關(guān)代理商/技術(shù)參數(shù) |
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| AK4358VQP-L | 功能描述:IC DAC 24BIT SERIAL 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
| AK4359 | 制造商:AKM 制造商全稱:AKM 功能描述:192 KHZ 24 BIT 8CH DAC |
| AK4359_06 | 制造商:AKM 制造商全稱:AKM 功能描述:106dB 192kHz 24-Bit 8ch DAC |
| AK4359A | 制造商:AKM 制造商全稱:AKM 功能描述:106dB 192kHz 24-Bit 8ch DAC |
| AK4359AEF | 制造商:AKM 制造商全稱:AKM 功能描述:106dB 192kHz 24-Bit 8ch DAC |
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