參數(shù)資料
型號(hào): AK4348VF
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: 3.3V 192kHz 24-Bit 8-Channel DAC
中文描述: 3.3 192kHz的24位8通道DAC
文件頁(yè)數(shù): 17/31頁(yè)
文件大小: 386K
代理商: AK4348VF
ASAHI KASEI
[AK4348]
MS0532-E-00
2006/07
- 17 -
Soft Mute Operation
Soft mute operation is performed in the digital domain. When the SMUTE bit goes to “1”, the output signal is attenuated
by -
during the ATT_DATA
×
ATT transition time (Table 10) from the current ATT level. When the SMUTE bit is
returned to “0”, the mute is cancelled and the output attenuation gradually changes to the ATT level during the
ATT_DATA
×
ATT transition time. If the soft mute is cancelled before attenuating to -
after starting the operation, the
attenuation is discontinued and returned to ATT level by the same cycle. The soft mute is effective when changing the
signal source without stopping the signal transmission.
SMUTE
Attenuation
DZF pin
ATT Level
-
AOUT
8192/fs
GD
(2)
GD
(1)
(3)
(4)
(1)
Notes:
(1) ATT_DATA
×
ATT transition time (Table 10). For example, in Normal Speed Mode, this time is 1020LRCK cycles
(1020/fs) at ATT_DATA=255.
(2) The analog output corresponding to the digital input has a group delay, GD.
(3) If the soft mute is cancelled before attenuating to -
after starting the operation, the attenuation is discontinued and
returned to ATT level by the same cycle.
(4) When the input data at each channel is continuously zero for 8192 LRCK cycles, the DZF pin of each channel goes
to “H”. The DZF pin immediately goes to “L” if input data are not zero after going DZF “H”. In parallel control
mode, the DZF pin is fixed to “L” regardless of the state of SMUTE pin.
Figure 11. Soft Mute and Zero Detection (DZFB bit = “0”)
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