參數(shù)資料
型號(hào): AK4346VF
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: 3.3V 192kHz 24-Bit 6-Channel DAC
中文描述: 3.3 192kHz的24位6通道DAC
文件頁數(shù): 18/31頁
文件大?。?/td> 379K
代理商: AK4346VF
ASAHI KASEI
[AK4346]
MS0531-E-00
2006/07
- 18 -
System Reset
The AK4346 should be reset once by bringing RSTB pin = ”L” upon power-up. The AK4346 is powered up and the
internal timing starts clocking by LRCK “
” after exiting reset and power down state by MCLK. The AK4346 is in the
power-down mode until MCLK and LRCK are input.
Power ON/OFF timing
All DACs are placed in the power-down mode by bringing RSTB pin “L” and the registers are initialized. The analog
outputs go to VCOM. Since some click noise occurs at the edge of the RSTB signal, the analog output should be muted
externally if the click noise influences system application.
Each DAC can be powered down by setting each power-down bit (PW1-3 bits) to “0”. In this case, the registers are not
initialized and the corresponding analog outputs go to VCOM. Since some click noise occurs at the edge of the RSTB
signal, the analog output should be muted externally if the click noise influences system application.
RSTB pin
Power
Reset
Normal Operation
Clock In
MCLK,LRCK,BICK
DAC In
(Digital)
DAC Out
(Analog)
External
Mute
Mute ON
(5)
DZF1/DZF2
Don’t care
“0”data
GD
(1)
(3)
(4)
(6)
GD
(3)
Mute ON
“0”data
Don’t care
Internal
State
(2)
(2)
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs are VCOM at the power-down mode.
(3) Click noise occurs at the edge of RSTB signal. This noise is output even if “0” data is input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (RSTB pin = “L”).
(5) Mute the analog output externally if the click noise (3) influences the system application.
The timing example is shown in this figure.
(6) DZF pins are “L” in the power-down mode (RSTB pin = “L”). (DZFB bit = “0”)
Figure 12. Power-down/up Sequence Example
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