參數(shù)資料
型號: AK4346VF
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: 3.3V 192kHz 24-Bit 6-Channel DAC
中文描述: 3.3 192kHz的24位6通道DAC
文件頁數(shù): 12/31頁
文件大?。?/td> 379K
代理商: AK4346VF
ASAHI KASEI
[AK4346]
MS0531-E-00
2006/07
- 12 -
Audio Serial Interface Format
In parallel control mode, the DIF0-1 and TDM0 pins can select eight serial data modes (Table 7). The register value of
DIF0-1 and TDM0bits are ignored. In serial control mode, the DIF0-2 and TDM0-1 bits shown in Table 8 can select 11
serial data modes. The default format is Mode 2 (24-bit MSB justified format in normal mode). The setting of DIF1 pin
is ignored. In all modes the audio data is MSB-first, 2’s complement format and is latched on the rising edge of BICK.
Mode 2 can be used for 16/20-bit MSB justified formats by zeroing the unused LSB’s.
In parallel control mode, when the TDM0 pin = “H”, the audio interface format is TDM256 mode (Table 7). The audio
data of all DACs (six channels) is input to the SDTI1 pin. The input data to SDTI2-3 pins is ignored. BICK should be
fixed to 256fs. “H” time and “L” time of LRCK should be at least 1/256fs. The audio data is MSB-first, 2’s complement
format. The input data to SDTI1 pin is latched on the rising edge of BICK.
In serial control mode, when the TDM0 bit = “1” and the TDM1 bit = “0”, the audio interface format is TDM256 mode
(Table 8), and the audio data of all DACs (six channels) is input to the SDTI1 pin. The input data to SDTI2-3 pins is
ignored. BICK should be fixed to 256fs. “H” time and “L” time of LRCK should be at least 1/256fs. The audio data is
MSB-first, 2’s complement format. The input data to SDTI1 pin is latched on the rising edge of BICK. In TDM128 mode
(TDM0 bit = “1” and TDM1 bit = “1”, Table 8), the audio data of DACs (four channels; L1, R1, L2, R2) is input to the
SDTI1 pin. The other two data (L3, R3) is input to the SDTI2 pin. The input data to SDTI3 pins is ignored. BICK should
be fixed to 128fs. The audio data is MSB-first, 2’s complement format. The input data to SDTI1-2 pins is latched on the
rising edge of BICK.
Mode
TDM0 DIF1
DIF0
SDTI Format
0
L
L
L
16-bit LSB Justified
1
L
L
H
20-bit LSB Justified
2
L
H
L
24-bit MSB Justified
3
L
H
H
24-bit I
2
S Compatible
H
L
L
N/A
H
L
H
N/A
5
H
H
L
24-bit MSB Justified
6
H
H
H
24-bit I
2
S Compatible
LRCK
H/L
H/L
H/L
L/H
BICK
32fs
40fs
48fs
48fs
256fs
256fs
Figure
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Normal
TDM256
Table 7. Audio Data Formats (Parallel control mode)
Mode
TDM1 TDM0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
DIF2
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
DIF1
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
DIF0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
SDTI Format
16-bit LSB Justified
20-bit LSB Justified
24-bit MSB Justified
24-bit I
2
S Compatible
24-bit LSB Justified
N/A
N/A
24-bit MSB Justified
24-bit I
2
S Compatible
24-bit LSB Justified
N/A
N/A
24-bit MSB Justified
24-bit I
2
S Compatible
24-bit LSB Justified
LRCK
H/L
H/L
H/L
L/H
H/L
BICK
32fs
40fs
48fs
48fs
48fs
256fs
256fs
256fs
128fs
128fs
128fs
Figure
Figure 1
Figure 2
Figure 3
Figure 4
Figure 2
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
0
1
2
3
4
5
6
7
8
9
10
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
Normal
TDM256
TDM128
Table 8. Audio Data Formats (Serial control mode, Default: Mode 2)
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