
ASAHI KASEI 
[AK4346] 
MS0531-E-00 
2006/07 
- 23 - 
Register Map
Addr 
Register Name 
00H 
Control 1 
01H 
Control 2 
02H 
Control 3 
03H 
LOUT1 ATT Control 
04H 
ROUT1 ATT Control  
05H 
LOUT2 ATT Control 
06H 
ROUT2 ATT Control  
07H 
LOUT3 ATT Control 
08H 
ROUT3 ATT Control  
09H 
Reserved 
0AH 
Reserved 
0BH 
Invert Output Signal 
0CH 
DZF1 Control 
0DH 
DZF2 Control 
0EH 
DEM Control 
Note: For addresses from 0FH to 1FH, data must not be written. 
When RSTB pin goes to “L”, the registers are initialized to their default values. 
When RSTN bit goes to “0”, the only internal timing is reset, and the registers are not initialized to their default 
values. All data can be written to the registers even if PW1-3 bits or RSTN bit is “0”. 
Register Definitions
Addr Register Name 
D7 
D6 
00H 
Control 1 
ACKS
TDM1
Default 
1 
0 
  RSTN: Internal timing reset 
0: Reset. All DZF pins go to “H” and any registers are not initialized. 
      1: Normal operation 
When MCLK frequency or DFS changes, the click noise can be reduced by RSTN bit. 
PW1: Power-down control (0: Power-down, 1: Power-up) 
PW1: Power down control of DAC1 
This bit is duplicated into D1 of 02H. 
DIF2-0: Audio data interface modes (See Table 7, Table 8) 
Initial: “010”, Mode 2  
TDM0-1: TDM Mode Select 
Mode 
TDM1 
TDM0
BICK 
Normal 
0 
0 
32fs
~
TDM256 
0 
1 
256fs fixed
TDM128 
1 
1 
128fs fixed
ACKS: Master Clock Frequency Auto Setting Mode Enable  
0: Disable, Manual Setting Mode 
1: Enable, Auto Setting Mode 
Master clock frequency is detected automatically when the ACKS bit = “1”. In this case, the setting of 
DFS1-0 bits is ignored. When this bit is “0”, DFS1-0 bits set the sampling speed mode. 
D7 
ACKS
0 
0 
ATT7
ATT7
ATT7
ATT7
ATT7
ATT7
1 
1 
INVL1
L1 
L1 
0 
D6 
D5 
D4 
DIF2 
DFS1 
0 
ATT4 
ATT4 
ATT4 
ATT4 
ATT4 
ATT4 
1 
1 
INVR2
R2 
R2 
0 
D3 
DIF1 
DFS0 
0 
ATT3
ATT3
ATT3
ATT3
ATT3
ATT3
1 
1 
INVL3
L3 
L3 
DEMA
D2 
DIF0 
DEM1 
DZFB 
ATT2 
ATT2 
ATT2 
ATT2 
ATT2 
ATT2 
1 
1 
INVR3 
R3 
R3 
DEMB 
D1 
PW1 
DEM0 
PW1 
ATT1 
ATT1 
ATT1 
ATT1 
ATT1 
ATT1 
1 
1 
0 
0 
0 
DEMC 
D0 
RSTN 
SMUTE
0 
ATT0 
ATT0 
ATT0 
ATT0 
ATT0 
ATT0 
1 
1 
0 
0 
0 
0 
TDM1
0 
PW3 
ATT6
ATT6
ATT6
ATT6
ATT6
ATT6
1 
1 
INVR1
R1 
R1 
0 
TDM0
SLOW
PW2 
ATT5
ATT5
ATT5
ATT5
ATT5
ATT5
1 
1 
INVL2
L2 
L2 
0 
D5 
TDM0
0 
D4 
DIF2 
0 
D3 
DIF1 
1 
D2 
DIF0 
0 
D1 
PW1 
1 
D0 
RSTN
1 
SDTI
1-3 
1 
1-2 
Sampling Speed 
Normal, Double, Quad Speed 
Normal Speed 
Normal, Double Speed