參數(shù)資料
型號(hào)： AK4319A
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： 18Bit SCF DAC
中文描述： 18位超臨界數(shù)模轉(zhuǎn)換器
文件頁(yè)數(shù)： 12/18頁(yè)
文件大小： 177K
代理商： AK4319A
ASAHI KASEI
[AK4319A]
M0011-E-01
1998/6
- 12 -
Power-Down
The AK4319A are placed in the power-down mode by bringing PD pin "L" and the analog outputs are
floating(Hi-Z). Figure 7 shows an example of the system timing at the power-down and power-up.
1
{
Analog output has the group delay(GD).
2
{
When power-down is initiated, analog outputs are set into Hi-Z. Output noise level is about
-110dB.
3
{
Some -50dB of click noise occurs at the transition("
↑↓
") of PD pin.
4
{
When the master clock is stopped, the AK4319A should have been in the power-down mode.
5
{
If the click noise(
3
{
)is a problem, an external mute circuit which generates above timing (
5
{
)is
needed. Please refer to Figure 7 .
Figure 7 . Power-down/up sequence example
System Reset
The AK4319A should be reset once by bringing PD "L" upon power-up. The AK4319A is powered up and
the internal timing starts clocking by LRCK "
↑
" after exiting reset and power down state by XTI. The
AK4319A is in power-down mode until LRCK is input.
External mute circuit
Some click noise may occur at the transition("
↑↓
") of PD signal. The click noise of PD signal can be
avoided by controlling the external mute circuit. The S/N of -110dB could be achieved by muting the
analog outputs using DZF signal.
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