參數(shù)資料
型號: AK4220
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: 7:3 Audio Switch and 6:3 Video Switch
中文描述: 7:3音頻交換機(jī)和6點(diǎn)03分視頻開關(guān)
文件頁數(shù): 9/33頁
文件大?。?/td> 537K
代理商: AK4220
I
[AK4220]
MS0627-E-00
2007/05
- 9 -
ANALOG CHARACTERISTICS (VIDEO)
(Ta=25
°
C; AVDD = VVDD1-2 = 5V, DVDD =3.3V; AVSS = VVSS1-3 = DVSS = 0V; unless otherwise specified)
Parameter
Conditions
Sync Tip Clamp Voltage
(Note: 12)
Gain (Note: 13)
Input=0.3Vp-p, 100kHz
Frequency Response (Note: 13)
Input=0.3Vp-p, 100kHz to 6MHz.
Maximum Input Signal
f=100kHz, maximum with distortion < 1.0%,
gain=6dB(typ).
Load Resistance
R1+R2(Note: 14)
Load Capacitance
C1 (Note: 14)
C2 (Note: 14)
Interchannel Isolation (Note: 15) f=4.43MHz, 1Vpp input.
S/N
Reference Level = 0.7Vpp, CCIR 567
weighting. BW= 15kHz to 5MHz.
Differential Gain
0.7Vpp 5steps modulated staircase.
chrominance &burst are 280mVpp, 4.43MHz.
Differential Phase
0.7Vpp 5steps modulated staircase.
chrominance &burst are 280mVpp, 4.43MHz.
Input Detection Circuit
Input Reception (Note: 16)
Note: 12. SAGN bit=“1”, DC output. There is no specification for using the Sag Compensation circuit (SAGN bit=“0”).
Sync Tip Clamp Voltage is proportional to AVDD voltage, VOUT=0.17 x AVDD V(typ).
Note: 13. If SAGN bit=“0” for using the Sag Compensation circuit, the measurement point is between C3 and R1 of
Figure 5. If SAGN bit=“1” for DC output, the measurement point is video output pin.
Note: 14. See Figure 5 and Figure 6.
Note: 15. Between all channels of VIN1-6.
Note: 16. If the input voltage is smaller than the detection reception value, the signal isn’t detected. If the input voltage is
larger than the detection reception value, the signal is detected. The input reception value is proportional to
AVDD voltage, 0.014 x AVDD Vpp(typ).
C3
100uF
min
-
typ
0.6
max
-
Units
V
At output pin.
5.5
-1.0
1.5
6
-
6.5
1.0
-
dB
dB
Vpp
150
-
-
Ω
pF
pF
dB
dB
400
15
-
-
-
-
50
74
-
±
0.4
-
%
-
±
0.9
-
Degree
0.04
0.07
0.1
Vpp
VOUT
R1
75
Ω
VFB
C4
2.2uF
+6dB
C2=C21+C22+C23= 15pF(max)
C1= 400pF(max)
R2
75
Ω
C21
C22
C23
C1
Figure 5. Load Resistance R1, R2 and Load Capacitance C1, C2 (SAGN bit=“0”, using the Sag Compensation circuit)
VOUT
R1
75
Ω
VFB
+6dB
C2=15pF(max)
C1=400pF(max)
R2
75
Ω
C2
C1
Figure 6. Load Resistance R1, R2 and Load Capacitance C1, C2 (SAGN bit=“1”, DC output)
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