
I 
[AK4220] 
MS0627-E-00 
2007/05 
- 30 - 
1. Grounding and Power Supply Decoupling 
The AK4220 requires careful attention to power supply and grounding arrangements. AVDD, VVDD1-2 and DVDD are 
usually supplied from the analog power supply in the system. Alternatively if AVDD, VVDD1-2  and DVDD are supplied 
separately, the power up sequence is not critical. AVSS, VVSS1-3 and DVSS must be connected to the analog ground 
plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto 
the printed circuit board. Decoupling capacitors should be as close to the AK4220 as possible, with the small value 
ceramic capacitors being the nearest. 
2. Voltage Reference 
VCOM is a signal ground of this chip. A 2.2
μ
F electrolytic capacitor in parallel with a 0.1
μ
F ceramic capacitor attached 
between VCOM and AVSS eliminates the effects of high frequency noise. No load current may be drawn from VCOM 
pin. All signals, especially clocks, should be kept away from VCOM in order to avoid unwanted coupling into the 
AK4220. MUTET is an audio output common voltage. A 0.1
μ
F electrolytic capacitor attached between VCOM and 
AVSS. No load current may be drawn from MUTET. All signals, especially clocks, should be kept away from MUTET in 
order to avoid unwanted coupling into the AK4220. 
3. The notes for drawing the board 
Analog input and output pins should be as short as possible in order to avoid unwanted coupling into the AK4220. The 
unused pins should be open.  
4. Video Output 
The AK4220 has on-chip 3ch video amp for drive 150
Ω
  resistance and two way to output video signal.  One way is using 
the Sag Compensation circuit (Figure 30), the other way is using DC output (Figure 31).  100
μ
F and 2.2
μ
F capacitors is 
needed for Sag Compensation circuit . It should be shorted VOUT pin and VBF pin using DC output mode. The clamp 
level is 600mV(typ) in the DC output mode.  Each output way can set by SAGN bit (Table 13).  
VOUT
R1 
75
Ω
VFB 
C3 
100uF
C4 
2.2uF
+6dB 
R2 
75
Ω
Figure 30. Video Block (SAGN bit=“0”, Sag Compensation mode) 
VOUT
R1 
75
Ω
VFB 
+6dB 
R2 
75
Ω
Figure 31. Video Block (SAGN bit=“1”, DC Output) 
SAGN bit 
0 
1 
Output  
Sag Compensation mode  
DC output mode 
(default) 
Table 13. Setting for the video output