
ASAHI KASEI
[AK4183]
 [WRITE Operations] 
The second byte that followed by address byte consists of the control command byte of the AK4183. The operational mode is 
determined by control command. The bit format is MSB first and 8 bits width. Control command is described in the Table 3. The 
AK4183 generates an acknowledge after each byte has been received. A control command transfer is terminated by a STOP 
condition or Repeated Start condition generated by the master. Refer to the Table 3 in detail. 
D7 
D6 
D5 
D4 
S 
A2 
A1 
A0 
MS0500-E-00 
 2006/04 
10
D3 
X1 
D2 
PD0 
D1 
D0 
X2 
MODE 
Figure 9  Control Command Byte 
S
R
Address 
Command 
S
A
A
A
A
S
P
SDA 
Figure 10 Single Write Transmission Sequence 
[READ Operation] 
The operation mode is determined by the write command just before read operation.  
AK4183 features two methods of read operation, single read operation and continuous read operation. The continuous read 
operation is a series of single read operation. Each single read operation in continuous read operation make AK4183 updated A/D 
conversion on each read operation. Write operation does not need to issue before each read operations are executed.  
The channel selection of AK4183 defines by the control command just before READ operation. When the address byte with R/W 
= “1”  read operations are executed.  A/D readout format is MSB first, 1byte or 2bytes width. Upper 8bits are valid on 8-bit mode 
and upper 12 bits are valid, and lower 4 bits are filled with zero on 12-bit mode.  
[Single READ mode]  
Read operation begins with START condition followed by the address byte with R/W= “1”.The address matches AK4183 generates 
ACK. And after transmission of the address byte, the master receives upper 8bit A/D data first, and generates ACK. The AK4183 
transmits the remaining 4-bit A/D data and followed by 4-bit zero data (12bit mode).  Master device receives 8bit A/D data (8bit 
mode). The master then generates NACK and stop condition or repeated start condition. 
S
A/D data 
A
A
S
N
A/D data 
SDA 
D
D
D
S 
P
A
M
M
D
Address 
R
Figure 11 Single A/D data Read Sequence (12-bit mode)