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參數(shù)資料
| 型號： | AK4140VF |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | Digital BTSC Decoder |
| 中文描述： | 數(shù)字BTSC解碼器 |
| 文件頁數(shù)： | 33/43頁 |
| 文件大?。?/td> | 538K |
| 代理商： | AK4140VF |
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ASAHI KASEI
[AK4140]
2. WRITE Operations
Set R/W bit = “0” for the WRITE operation of the AK4140.
After receipt the start condition and the first byte, the AK4140 generates an acknowledge, and awaits the second byte
(register address). The second byte consists of the address for control registers of AK4140. The format is MSB first, and
those most significant 3-bits are “Don’t care”.
*
*
*
A4
A3
A2
A1
A0
(*: Don’t care)
Figure 20. The Second Byte
After receipt the second byte, the AK4140 generates an acknowledge, and awaits the third byte. Those data after the
second byte contain control data. The format is MSB first, 8bits.
D7
D6
D5
D4
D3
D2
D1
D0
Figure 21. Byte structure after the second byte
The AK4140 is capable of more than one byte write operation by one sequence.
After receipt of the third byte, the AK4140 generates an acknowledge, and awaits the next data again. The master can
transmit more than one words instead of terminating the write cycle after the first data word is transferred. After the
receipt of each data, the internal 5bits address counter is incremented by one, and the next data is taken into next address
automatically. If the address exceed 08H prior to generating the stop condition, the address counter will “roll over” to 00H
and the previous data will be overwritten.
S
T
A
R
T
SDA
A
C
K
A
C
K
S
Slave
Address
A
C
K
Register
Address(n)
Data(n)
P
S
T
O
P
Data(n+x)
A
C
K
Data(n+1)
Figure 22. WRITE Operation
MS0547-E-01
2007/03
- 33 -
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