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參數(shù)資料
| 型號： | AK4140VF |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | Digital BTSC Decoder |
| 中文描述： | 數(shù)字BTSC解碼器 |
| 文件頁數(shù)： | 13/43頁 |
| 文件大?。?/td> | 538K |
| 代理商： | AK4140VF |
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ASAHI KASEI
[AK4140]
OPERATION OVERVIEW
System reset and Power-down Mode
The AK4140 should be reset once by bringing PDN PIN = “L” upon power-up.
PDN pin: Power down pin
“H”: Normal operation
“L”: Device power down & reset.
System Clock
The external clocks required to operate the AK4140 are MCLK, LRCK and SCLK. The AK4140 supports 256fs, 384fs,
512fs and 768fs as master clock (MCLK). The CKS1/0 bits select MCLK frequency. The AK4140 should be reset by
PDN pin= “L” after threse clocks are provided. If the external clocks are not present, place the AK4140 in power-down
mode. After exiting reset at power-up etc., the AK4140 remains in power-down mode until MCLK and LRCK are input.
MCLK
fs
256fs
384fs
512fs
32.0kHz
8.1920MHz
12.2880MHz
16.3840MHz
44.1kHz
11.2896MHz
16.9344MHz
22.5792MHz
48.0kHz
12.2880MHz
18.4320MHz
24.5760MHz
Table 1. System clock example (Slave mode)
CKS1
bit
bit
0
0
0
1
1
0
1
1
Table 2. Master clock frequency select
Audio Interface Format
The AK4140 supports 16 types of audio data interface selected by the TDM1-0, DIF bits and M/S pin as shown in Table
3. In all formats the serial data is MSB-first, 2's compliment format. The SDTO is clocked out on the falling edge of
SCLK.
In normal mode, Mode 0-1 are the slave mode, and SCLK is available up to 128fs. SCLK outputs 64fs clock in Mode 2-3.
In TDM256 mode, SCLK should be fixed to 256fs. In the slave mode, “H” time and “L” time of LRCK should be 1/256fs
at least. In the master mode, “H” time (“L” time at I
2
S mode) of LRCK is 1/8fs typically.
In TDM128A mode, SCLK should be fixed to 128fs. In the slave mode, “H” time and “L” time of LRCK should be
1/128fs at least. In the master mode, “H” time (“L” time at I
2
S mode) of LRCK is 1/4fs typically.
In TDM128B mode, SCLK should be fixed to 128fs. In the slave mode, “H” time and “L” time of LRCK should be
1/128fs at least. In the master mode, “H” time (“L” time at I
2
S mode) of LRCK is 1/8fs typically.
SCLK
768fs
64fs
128fs
24.576MHz
33.8688MHz
36.8640MHz
2.0480MHz
2.8224MHz
3.0720MHz
4.0960MHz
5.6448MHz
6.1440MHz
CKS0
MCLK
256fs
384fs
512fs
768fs
(default)
MS0547-E-01
2007/03
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