參數(shù)資料
型號: AK4140
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: Digital BTSC Decoder
中文描述: 數(shù)字BTSC解碼器
文件頁數(shù): 8/43頁
文件大?。?/td> 538K
代理商: AK4140
ASAHI KASEI
[AK4140]
Parameter
Audio Interface Timing (Master mode)
Normal mode (TDM1=“L”, TDM0=“L”)
SCLK Frequency
SCLK Duty
SCLK “
” to LRCK
SCLK “
” to SDTO
TDM256 mode (TDM1=“L”, TDM0=“H”)
SCLK Frequency
SCLK Duty (Note 7)
SCLK “
” to LRCK
SCLK “
” to SDTO
TDMIN Hold Time
TDMIN Setup Time
TDM128 mode (TDM1=“H”, TDM0=“H”)
SCLK Frequency
SCLK Duty
SCLK “
” to LRCK
SCLK “
” to SDTO
TDMIN Hold Time
TDMIN Setup Time
Power-Down & Reset Timing
PDN Pulse Width (Note 8)
PDN “
” to SDTO valid (Note 9)
Note 6. SCLK rising edge must not occur at the same time as LRCK edge.
Note 7. This value is MCLK=512fs. Duty cycle is not guaranteed when MCLK=256fs/384fs.
Note 8. The AK4140 can be reset by bringing the PDN pin = “L”.
Note 9. This cycle is the number of LRCK rising edges from the PDN pin = “H”.
Parameter
Control Interface Timing (I
2
C Bus):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time
(prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 10)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise
Suppressed by Input Filter
Capacitive load on bus
Note 10. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Symbol
fBCK
dBCK
tMBLR
tBSD
fBCK
dBCK
tMBLR
tBSD
tSDH
tSDS
fBCK
dBCK
tMBLR
tBSD
tSDH
tSDS
tPD
tPDV
min
20
40
12
20
10
10
12
20
10
10
150
typ
64fs
50
256fs
50
128fs
50
516
max
20
40
12
20
12
20
Units
Hz
%
ns
ns
Hz
%
ns
ns
ns
ns
Hz
%
ns
ns
ns
ns
ns
1/fs
Symbol
Min
-
1.3
0.6
1.3
0.6
0.6
0
0.1
-
-
0.6
0
0
typ
max
400
-
-
-
-
-
-
-
0.3
0.3
-
50
400
Units
kHz
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
ns
pF
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
Cb
MS0547-E-01
2007/03
- 8 -
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