參數(shù)資料
型號: AK4127VF
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: 192kHz / 24Bit High Performance Asynchronous SRC
中文描述: 192kHz的/ 24位高性能異步鋼骨混凝土
文件頁數(shù): 15/29頁
文件大?。?/td> 489K
代理商: AK4127VF
[AK4127]
ILRCK
IBICK(64fs)
0 1 2
24
31 0 1 2
1
0
31
24
8 9
8 9
SDTI(i)
Don't Care
0
8
1 0
23:MSB, 0:LSB
Lch Data
Rch Data
23
8
Don't Care
23
1
Figure 5. Mode 4 Timing
System Clock & Audio Interface Format for Output PORT
The output port works in master mode or slave mode. The MCLK is not needed in slave mode. The CMODE2-0 pins
select the master/slave and bypass mode. The CMODE2-0 pins should be controlled when the PDN pin = “L”.
The ODIF1-0 pins and OBIT1-0 pins select the audio interface format for the output port. The audio data is MSB first, 2’s
compliment format. The SDTO is clocked out on the falling edge of OBICK. Select the audio interface format when the
PDN pin = “L”. When in BYPASS mode, both IBICK and OBICK are fixed to 64fs.
When the PLL2-0 pin= “L/H/H”, setting the output port slave (CMODE2-0pin = “H/L/L” or “H/H/L”) enables the TDM
mode at the output port. The OMCLK pin changes to TDMIN pin for TDM data input in TDM mode.
CMODE
2
1
0
L
L
L
Master
1
L
L
H
Master
2
L
H
L
Master
3
L
H
H
Master
CMODE
Mode
CMODE0
Master / Slave
OMCLK
fso
256fso
384fso
512fso
768fso
8k
108kHz
8k
108kHz
8k
54kHz
8k
54kHz
4
H
L
L
Slave
Not used. Set to DVSS.
Note 15)
(
128fso
Not used. Set to DVSS.
Note 15)
(
Not used. Set to DVSS.
8k
216kHz
5
H
L
H
Master
8k
216kHz
6
H
H
L
Slave (Bypass)
8k
216kHz
7
H
H
H
Master (Bypass)
8k
216kHz
Note 15. Changed to TDMIN pin when PLL2-0 pins = “L/H/H”.
Table 3. Master/Slave Control (Output PORT)
Mode
0
1
2
3
ODIF1
L
L
H
H
ODIF0
L
H
L
H
SDTO Format
LSB justified
(Reserved)
MSB justified
I
2
S Compatible
Table 4. Output Audio Interface Format 1 (Output PORT)
MS0593-E-01
2007/07
- 15 -
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