參數(shù)資料
型號(hào)： AK4116VN
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： Low Power 48kHz Digital Audio Receiver
中文描述： 低功率48kHz的數(shù)字音頻接收器
文件頁(yè)數(shù)： 10/37頁(yè)
文件大?。?/td> 372K
代理商： AK4116VN
ASAHI KASEI
[AK4116]
MS0156-E-03
2005/08
- 10 -
OPERATION OVERVIEW
Non-PCM (AC-3, MPEG, etc.) and DTS-CD Bitstream Detection
The AK4116 has a Non-PCM steam auto-detection function. When the 32-bit mode Non-PCM preamble based on Dolby
“AC-3 Data Stream in IEC60958 Interface” is detected, the NPCM bit goes to “1”. The 96-bit sync code consists of
0x0000, 0x0000, 0x0000, 0x0000, 0xF872 and 0x4E1F. Detection of this pattern will set the NPCM to “1”. Once the
NPCM is set to “1”, it will remain “1” until 4096 frames pass through the chip without an additional sync pattern being
detected (Timing diagram: Figure 26 and Figure 27). When those preambles are detected, the burst preambles Pc (burst
information: Table 8) and Pd (length code: Table 9) that follow those sync codes are stored to registers. The AK4116 also
has a DTS-CD bitstream auto-detection function. When AK4116 detects DTS-CD bitstreams, the DTSCD bit goes to “1”.
If the next sync code does not occur within 4096 frames, the DTSCD bit goes to “0” until either the AK4116 detects the
stream again. OR’ed value of the NPCM and DTSCD bits are output to the AUTO bit. The AK4116 detects 14bit sync
word of a DTS-CD bitstearm, while it does not detect 16bit sync word (0x7FFE8001).
Clock Recovery
The on-chip, low jitter PLL has a wide lock range of 32kHz to 48kHz and a lock time of less than 20ms. The AK4116 has
a sampling frequency detect function (32kHz, 44.1kHz and 48kHz) that uses either clock comparison against the X’tal
oscillator or the channel status information. The PLL loses lock when the received sync interval is incorrect.
Clock Operation Mode
The AK4116 has two sources for MCKO and SDTO.
1) MCKO and SDTO source is recovered by PLL from RX input.
2) MCKO source is X’tal or External clock. SDTO source is DAUX input.
The CM1-0 bits select the clock operation mode (Table 1). In Mode 2, the clock source is switched from PLL to X'tal
when the PLL loses lock. In Mode3, even though the clock source is fixed to X'tal, the PLL is also operating. This allows
the monitoring of recovered data such as C bits. For Mode2 and 3, it is recommended that the X’tal frequency and PLL
recovery frequency be set differently.
Mode
CM1
CM0
UNLCK
PLL
0
0
0
-
ON
1
0
1
-
OFF
0
ON
2
1
0
1
ON
3
1
1
-
ON
ON: Oscillation (Power-up), OFF: STOP (Power-down)
Note : When the X’tal is not used as clock comparison for fs detection (i.e. XTL1,0= “1,1”), the X’tal is off.
Table 1. Clock Operation Mode select
X'tal
ON(Note)
ON
ON
ON
ON
Clock source
PLL
X'tal
PLL
X'tal
X'tal
SDTO
RX
DAUX
RX
DAUX
DAUX
Default
相關(guān)PDF資料
PDF描述
AK4120 Sample Rate Converter with Mixer and Volume
AK4121A Asynchronous Sample Rate Converter
AK4121AVF Asynchronous Sample Rate Converter
AK4121 ASYNCHRONOUS SAMPLE RATE CONVERTER
AK4125VF 192kHz / 24Bit High Performance Asynchronous SRC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AK4116VNP-L 制造商:Asahi Kasei Microsystems Co Ltd 功能描述:
AK4117 制造商:AKM 制造商全稱:AKM 功能描述:Low Power 192kHz Digital Audio Receiver
AK4117_10 制造商:AKM 制造商全稱:AKM 功能描述:Low Power 192kHz Digital Audio Receiver
AK4117VF 制造商:AKM 制造商全稱:AKM 功能描述:Low Power 192kHz Digital Audio Receiver
AK4117VFP-E2 功能描述:IC RCVR DGTL AUD 24VSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:- 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*