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參數(shù)資料
| 型號： | AK4112A |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | High Feature 96kHz 24bit DIR |
| 中文描述： | 高功能96kHz的24位迪爾 |
| 文件頁數(shù)： | 19/31頁 |
| 文件大?。?/td> | 304K |
| 代理商： | AK4112A |
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ASAHI KASEI
[AK4112A]
MS0020-E-00
2000/3
- 19 -
n
Audio Serial Interface Format
The DIF0, DIF1 and DIF2 pins as shown in Table 13 can select eight serial data formats. In all formats the serial data is
MSB-first, 2's compliment format. The SDTO is clocked out on the falling edge of BICK and the DAUX is latched on
the rising edge of BICK. BICK outputs 64fs clock in Mode 0-5. Mode 6-7 are Slave Modes, and BICK is available up to
128fs at fs=48kHz. In the format equal or less than 20bit (Mode0-2), LSBs in sub-frame are truncated. In Mode 3-7, the
last 4LSBs are auxiliary data (see Figure 5).
When the Parity Error, Biphase Error or Frame Length Error occurs in a sub-frame, AK4112A continues to output the
last normal sub-frame data from SDTO repeatedly until the error is removed. When the Unlock Error occurs, AK4112A
output “0” from SDTO. In case of using DAUX pin, the data is transformed and output from SDTO. DAUX pin is used
in Clock Operation Mode 1, 3 and unlock state of Mode 2.
The input data format to DAUX should be left justified except in Mode5 and 7(Table 13). In Mode5 or 7, both the input
data format of DAUX and output data format of SDTO are I
2
S. Mode6 and 7 are Slave Mode that is corresponding to the
Master Mode of Mode4 and 5. In salve Mode, LRCK and BICK should be fed with synchronizing to MCKO1/2.
The initial state of the audio format is the Master Mode upon the power-up. Therefore, if the audio format is changed to
the Slave Mode after power-up, the setting of the external clocks should be careful until completing to set the control
registers.
0
3 4
7 8
11 12
27 28 29 30 31
preamble
Aux.
LSB
MSB
V U C P
sub-frame of IEC958
0
23
AK4112 Audio Data (MSB First)
LSB
MSB
Figure 5. Bit configuration
LRCK
BICK
Mode
DIF2
DIF1
DIF0
DAUX
SDTO
I/O
O
O
O
O
O
O
I
I
I/O
O
O
O
O
O
O
I
I
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, I
2
S
24bit, Left justified
24bit, I
2
S
16bit, Right justified
18bit, Right justified
20bit, Right justified
24bit, Right justified
24bit, Left justified
24bit, I
2
S
24bit, Left justified
24bit, I
2
S
H/L
H/L
H/L
H/L
H/L
L/H
H/L
L/H
64fs
64fs
64fs
64fs
64fs
64fs
Default
64-128fs
64-128fs
Table 13. Audio data format
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK4112AVF | Circular Connector; No. of Contacts:5; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:14; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:14-5 RoHS Compliant: No |
| AK4113-B | 192kHz digital audio receiver |
| AK4115VQ | High Feature 192kHz 24bit Digital Audio Interface Transceiver |
| AK4115 | High Feature 192kHz 24bit Digital Audio Interface Transceiver |
| AK4116VN | Low Power 48kHz Digital Audio Receiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4112AVF | 制造商:AKM 制造商全稱:AKM 功能描述:High Feature 96kHz 24bit DIR |
| AK4112B | 制造商:AKM 制造商全稱:AKM 功能描述:HIGH FEATURE 96kHz 24BIT DIR |
| AK4112B_12 | 制造商:AKM 制造商全稱:AKM 功能描述:High Feature 96kHz 24bit DIR |
| AK4112BVF | 功能描述:IC RCVR DGTL AUD QUAD 28VSOP 制造商:akm semiconductor inc. 系列:- 包裝:剪切帶（CT） 零件狀態(tài):過期 功能:音頻接收器 應(yīng)用:數(shù)字音頻接口 通道數(shù):4 接口:I2S 電壓 - 電源:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C（TA） 規(guī)格:22kHz ~ 108kHz 封裝/外殼:28-LSSOP（0.220"，5.60mm 寬） 供應(yīng)商器件封裝:28-VSOP 標(biāo)準(zhǔn)包裝:1 |
| AK4112BVFP | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述:HIGH FEATURE 96KHZ 24-BIT DIR |
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