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參數(shù)資料
| 型號： | AK4112A |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | High Feature 96kHz 24bit DIR |
| 中文描述： | 高功能96kHz的24位迪爾 |
| 文件頁數(shù)： | 10/31頁 |
| 文件大小： | 304K |
| 代理商： | AK4112A |
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ASAHI KASEI
[AK4112A]
MS0020-E-00
2000/3
- 10 -
OPERATION OVERVIEW
n
Non-PCM (AC-3, MPEG, etc.) Stream Detect
The AK4112A has a Non-PCM steam auto detect function. When the 32bit mode Non-PCM preamble based on Dolby
“AC-3 Data Stream in IEC958 Interface” is detected, the AUTO goes “H”. The 96bit sync code consists of 0x0000,
0x0000, 0x0000, 0x0000, 0xF872 and 0x4E1F. Detection of this pattern will set the AUTO “H”. Once the AUTO is set
“H”, it will remain “H” until 4096 frames pass through the chip without additional sync pattern being detected. When
those preambles are detected, the burst preambles Pc and Pd that follow those sync codes are stored to registers 0DH-
10H.
n
Clock Recovery and 96kHz Detect
On chip low jitter PLL has a wide lock range with 22kHz to 108kHz and the lock time is less than 20ms. The 96kHz
detect output pin FS96 goes “H” when the sampling rate is 88.2kHz or more and “L” at 54kHz or less. In X’tal Mode, the
FS96 pin outputs the value which is set by XFS96. PLL loses lock when the received sync interval is incorrect.
n
Master Clock
The AK4112A has two clock outputs, MCKO1 and MCKO2. These clocks are derived from either the recovered clock or
from the X'tal oscillator. The frequencies of the master clock outputs (MCKO1 & MCKO2) are set by OCKS0 and
OCKS1 as shown in Table 1. 96kHz sampling is not supported at No.2.
No.
0
1
2
3
OCKS1
0
0
1
1
OCKS0
0
1
0
1
MCKO1
256fs
256fs
512fs
MCKO2
256fs
128fs
256fs
X’tal
256fs
256fs
512fs
fs (kHz)
32, 44.1, 48, 96
32, 44.1, 48, 96
32, 44.1, 48
Defalt
Test Mode
Table 1. Master clock frequencies select
n
Clock Operation Mode
The CM0 and CM1 select the clock source of MCKO1/2 and the data source of SDTO via the dedicated pins or the
control register. In Mode 2, the clock source is switched from PLL to X'tal when PLL goes unlock state. In Mode3, the
clock source is fixed to X'tal, but PLL is also operating and the recovered data such as C bits can be monitored.
Mode
0
1
CM1
0
0
CM0
0
1
UNLOCK
PLL
ON
OFF
ON
ON
ON
X'tal
OFF
ON
ON
ON
ON
Clock source
PLL
X'tal
PLL
X'tal
X'tal
FS96
SDTO
RX
DAUX
RX
DAUX
DAUX
-
-
0
1
-
RFS96
XFS96
RFS96
XFS96
XFS96
Default
2
1
0
3
1
1
ON: Oscillation (Power-up), OFF: STOP (Power-down)
Table 2. Clock Operation Mode select
相關PDF資料 |
PDF描述 |
|---|---|
| AK4112AVF | Circular Connector; No. of Contacts:5; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:14; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:14-5 RoHS Compliant: No |
| AK4113-B | 192kHz digital audio receiver |
| AK4115VQ | High Feature 192kHz 24bit Digital Audio Interface Transceiver |
| AK4115 | High Feature 192kHz 24bit Digital Audio Interface Transceiver |
| AK4116VN | Low Power 48kHz Digital Audio Receiver |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AK4112AVF | 制造商:AKM 制造商全稱:AKM 功能描述:High Feature 96kHz 24bit DIR |
| AK4112B | 制造商:AKM 制造商全稱:AKM 功能描述:HIGH FEATURE 96kHz 24BIT DIR |
| AK4112B_12 | 制造商:AKM 制造商全稱:AKM 功能描述:High Feature 96kHz 24bit DIR |
| AK4112BVF | 功能描述:IC RCVR DGTL AUD QUAD 28VSOP 制造商:akm semiconductor inc. 系列:- 包裝:剪切帶（CT） 零件狀態(tài):過期 功能:音頻接收器 應用:數(shù)字音頻接口 通道數(shù):4 接口:I2S 電壓 - 電源:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C（TA） 規(guī)格:22kHz ~ 108kHz 封裝/外殼:28-LSSOP（0.220"，5.60mm 寬） 供應商器件封裝:28-VSOP 標準包裝:1 |
| AK4112BVFP | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述:HIGH FEATURE 96KHZ 24-BIT DIR |
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