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參數(shù)資料
| 型號(hào)： | AK2303LV |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:15; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:14; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:14-15 RoHS Compliant: No |
| 中文描述： | 雙交換機(jī)的PCM編解碼器的模擬線路卡 |
| 文件頁數(shù)： | 9/41頁 |
| 文件大小： | 559K |
| 代理商： | AK2303LV |
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ASAHI K ASEI
[AK 2303LV]
FUNCTIONAL DESCRIPTION
PCM Data Interface
AK2303LV supports the following 3 PCM data formats
Long Frame Sync(LF)
Short Frame Sync(SF)
GCI
PCM data of both channels are multiplexed and interfaced through the common pins(DR,DX).The first 8bit is defined as B1
channel and the seconds 8bit is defined as B2 channel in the PCM data stream.
The order of PCM data is MSB first in each channel.
Selection of the interface mode
The GCI and ordinary PCM interface(LF,SF) are selectable through the CPU register as following table.
Either LF or SF is automatically selected by means of detecting the length of 8KHz frame signal in AK2303LV when PCM I/F
is set to “0”.
Register for PCM Interface mode select(Address:100 Bit:5)
PCMIF
PCM Interface
2303-E -00 9 2001/09
Comments
0
LF or SF
LF/SF are selected automatically
1
GCI
Default value after power-on reset =LF/SF mode(PCMIF=0).
LONG FRAME( LF ) / SHORT FRAME ( SF )
Automatic LF/SF selection
AK2303LV monitors the duration of the FS “H” level and selects either LF or SF interface format automatically.
Period of FS=”H”
Interface format
more than 2 clocks of BCLK
LF
1 clock of BCLK
SF
Timing of the interface
16 bits PCM data (B1 and B2) is accommodated in 1 frame (125us) defined by 8kHz frame sync signal.
Although there are 32 time slots at maximum in 8kHz frame (when BCLK=4.096MHz), PCM data for AK2303LV occupy one
time slot for channel 0 and channel 1, as is indicated in following.
Frame Sync signal (FS)
8kHz reference signal. This signal indicated the timing and the frame position of 8kHz PCM interface.
Bit Clock (BCLK)
BCLK defines the PCM data rate. BCLK can be varied 4.096, 2.048MHz. All internal clock of the LSI is generated based on
this BCLK signal.
Register for BCLK frequency select(Address:101 Bit:7,6)
CLKSEL[1:0]
BCLK frequency
comments
00
Reserved
01
Reserved
10
2.048MHz
Default value
11
4.096MHz
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