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參數(shù)資料
| 型號： | AK2303LV |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:15; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:14; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:14-15 RoHS Compliant: No |
| 中文描述： | 雙交換機的PCM編解碼器的模擬線路卡 |
| 文件頁數(shù)： | 6/41頁 |
| 文件大?。?/td> | 559K |
| 代理商： | AK2303LV |
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ASAHI K ASEI
[AK 2303LV]
PIN FUNCTION
Pin# Name
I/O
1
TEST
I
TEST MODE setting (Please tie to AVSS)
0: Normal mode 1: Test mode
2
VFTN1
Transmit gain is defined by the ratio of R2/R1.
R1 is the external input resister connected to this pin.
R2 is the external feedback resister connected between this pin and GST1.
3
GST1
O
Output of the transmit OPamp(AMPT1) for channel 1.
4
GSR1
O
Output of the receive OPamp(AMPR1) for channel 1.
5
VFR1
Receive gain is defined by the ratio of R4/R3.
R3 is the external input resister connected to this pin.
R4 is the external feedback resister connected between this pin and VR1.
6
VR1
O
Analog Output equivalent to the received PCM data for channel 1.
7
ALAWN
I
A-law/u-law Select
0
：
A-law 1
：
u-law
8
AVDD
-
Positive supply voltage for analog circuit.
+3.3V supply.
9
DVDD
-
Positive supply voltage for digital circuit.
+3.3V supply.
2303-E -00 6 2001/09
10
FS
I
Frame sync input.
FS must be 8kHz clock which is synchronized with BCLK.
Bit clock of PCM data interface.
This clock is input for the internal PLL which gerenates the internal system clocks.
This clock defines the input/output data rate of DX and DR.
The frequency of BCLK should be 2.048MHz or 4.096MHz set via CPU register..
Serial output of PCM data.
The channel 1 data is output following the channel 0 data. The PCM data rate is
synchronized with BCLK. This output remains in the high impedance state except for the
period of transmitting PCM data.
Serial input of PCM data.
The channel 1 data is received following the channel 0 data. The PCM data rate is
synchronized with BCLK.
CH1 mute setting
0
：
mute 1
：
normal operation
CH0 mute setting
0
：
mute 1
：
normal operation
Clock input of serial interface.
I/O
Data input of serial interface.
I
Read and write enable of serial interface.
O
Pin for PLL loop filter.
External capacitance(Min 0.22uF) should be connected between this pin and AVSS.
11
BCLK
I
12
DX
13
DR
I
14
MUTE1
I
15
MUTE0
I
16
17
18
19
SCLK
DATA
CSN
LPC
I
Function
I
Negative analog input of the transmit OPamp(AMPT1) for channel 1.
I
Negative analog input of the receive OPamp(AMTR1) for channel 1.
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| AK2305 | Dual PCM CODEC for ISDN TERMINAL ADAPTER |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK2303LVM | 制造商:AKM 制造商全稱:AKM 功能描述:PBX???è￡??????￠?????-??°?????¤??3???????????¨????????￡??3?????? ??°??￡??-??3???????????ˉ ?????3??? |
| AK2304 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:A-Law/u-Law CODEC |
| AK2304A | 制造商:AKM 制造商全稱:AKM 功能描述:QUAD PCM CODEC/FILTER COMBO LSI |
| AK2305 | 制造商:AKM 制造商全稱:AKM 功能描述:Dual PCM CODEC for ISDN TERMINAL ADAPTER |
| AK2306 | 制造商:AKM 制造商全稱:AKM 功能描述:Dual PCM CODEC for ISDN/VoIP TERMINAL ADAPTER |
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