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鍨嬭櫉(h脿o)锛� AGLN125V5-ZVQG100I
寤犲晢锛� Microsemi SoC
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 113/150闋�(y猫)
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鎻忚堪锛� IC FPGA NANO 1KB 125K 100VQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 90
绯诲垪锛� IGLOO nano
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 3072
RAM 浣嶇附瑷�(j矛)锛� 36864
杓稿叆/杓稿嚭鏁�(sh霉)锛� 71
闁€(m茅n)鏁�(sh霉)锛� 125000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤�(l猫i)鍨嬶細 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 100-TQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 100-VQFP锛�14x14锛�
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IGLOO nano Low Power Flash FPGAs
Revision 17
2-49
Output Enable Register
Timing Characteristics
1.5 V DC Core Voltage
Figure 2-16 Output Enable Register Timing Diagram
50%
Preset
Clear
EOUT
CLK
D_Enable
50%
tOESUDtOEHD
50%
tOECLKQ
1
0
tOERECPRE
tOEREMPRE
tOERECCLR
tOEREMCLR
tOEWCLR
tOEWPRE
tOEPRE2Q
tOECLR2Q
tOECKMPWH tOECKMPWL
50%
Table 2-76 Output Enable Register Propagation Delays
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V
Parameter
Description
Std. Units
tOECLKQ
Clock-to-Q of the Output Enable Register
0.75
ns
tOESUD
Data Setup Time for the Output Enable Register
0.51
ns
tOEHD
Data Hold Time for the Output Enable Register
0.00
ns
tOECLR2Q
Asynchronous Clear-to-Q of the Output Enable Register
1.13
ns
tOEPRE2Q
Asynchronous Preset-to-Q of the Output Enable Register
1.13
ns
tOEREMCLR
Asynchronous Clear Removal Time for the Output Enable Register
0.00
ns
tOERECCLR
Asynchronous Clear Recovery Time for the Output Enable Register
0.24
ns
tOEREMPRE
Asynchronous Preset Removal Time for the Output Enable Register
0.00
ns
tOERECPRE
Asynchronous Preset Recovery Time for the Output Enable Register
0.24
ns
tOEWCLR
Asynchronous Clear Minimum Pulse Width for the Output Enable Register
0.19
ns
tOEWPRE
Asynchronous Preset Minimum Pulse Width for the Output Enable Register
0.19
ns
tOECKMPWH Clock Minimum Pulse Width HIGH for the Output Enable Register
0.31
ns
tOECKMPWL
Clock Minimum Pulse Width LOW for the Output Enable Register
0.28
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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