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鍨嬭櫉锛� AGLN125V5-ZCSG81I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 64/150闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA NANO 1KB 125K 81-CSP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 640
绯诲垪锛� IGLOO nano
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 3072
RAM 浣嶇附瑷�(j矛)锛� 36864
杓稿叆/杓稿嚭鏁�(sh霉)锛� 60
闁€鏁�(sh霉)锛� 125000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 81-WFBGA锛孋SBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 81-CSP锛�5x5锛�
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IGLOO nano DC and Switching Characteristics
2-4
Revision 17
PLL Behavior at Brownout Condition
Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper power-
up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed brownout
activation levels (see Figure 2-1 and Figure 2-2 on page 2-5 for more details).
When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V 卤 0.25
V for V5 devices, and 0.75 V 卤 0.2 V for V2 devices), the PLL output lock signal goes LOW and/or the
output clock is lost. Refer to the "Brownout Voltage" section in the "Power-Up/-Down Behavior of Low
Power Flash Devices" chapter of the IGLOO nano FPGA Fabric User鈥檚 Guide for information on clock
and lock recovery.
Internal Power-Up Activation Sequence
1. Core
2. Input buffers
3. Output buffers, after 200 ns delay from input buffer activation
To make sure the transition from input buffers to output buffers is clean, ensure that there is no path
longer than 100 ns from input buffer to output buffer in your design.
Figure 2-1 V5 Devices 鈥� I/O State as a Function of VCCI and VCC Voltage Levels
Region 1: I/O buffers are OFF
Region 2: I/O buffers are ON.
I/Os are functional but slower because
VCCI / VCC are below specification. For the
same reason, input buffers do not meet
VIH/VIL levels, and output buffers to not
meet VOH / VOL levels.
Min VCCI datasheet specification
voltage at a selected I/O
standard; i.e., 1.425 V or 1.7 V
or 2.3 V or 3.0 V
VCC
VCC = 1.425 V
Region 1: I/O Buffers are OFF
Activation trip point:
Va = 0.85 V 卤 0.25 V
Deactivation trip point:
Vd = 0.75 V 卤 0.25 V
Activation trip point:
Va = 0.9 V 卤 0.3 V
Deactivation trip point:
Vd = 0.8 V 卤 0.3 V
VCC = 1.575 V
Region 5: I/O buffers are ON
and power supplies are within
specification.
I/Os meet the entire datasheet
and timer specifications for
speed, VIH / VIL , VOH / VOL , etc.
Region 4: I/O
buffers are ON.
I/Os are functional
but slower because VCCI
is below specification. For the
same reason, input buffers do not
meet VIH / VIL levels, and output
buffers do not meet VOH/VOL levels.
where VT can be from 0.58 V to 0.9 V (typically 0.75 V)
VCCI
Region 3: I/O buffers are ON.
I/Os are functional; I/O DC
specifications are met,
but I/Os are slower because
the VCC is below specification.
VCC = VCCI + VT
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