Revision 17 2-47 Output Register Timing Characteristics 1.5 V DC Core Voltage Figure 2-15" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� AGLN125V5-ZCSG81I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 111/150闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA NANO 1KB 125K 81-CSP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 640
绯诲垪锛� IGLOO nano
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 3072
RAM 浣嶇附瑷�(j矛)锛� 36864
杓稿叆/杓稿嚭鏁�(sh霉)锛� 60
闁€鏁�(sh霉)锛� 125000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 81-WFBGA锛孋SBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 81-CSP锛�5x5锛�
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IGLOO nano Low Power Flash FPGAs
Revision 17
2-47
Output Register
Timing Characteristics
1.5 V DC Core Voltage
Figure 2-15 Output Register Timing Diagram
Clear
DOUT
CLK
Data_out
Preset
50%
tOSUD tOHD
50%
tOCLKQ
1
0
tORECPRE
tOREMPRE
tORECCLR
tOREMCLR
tOWCLR
tOWPRE
tOPRE2Q
tOCLR2Q
tOCKMPWH tOCKMPWL
50%
Table 2-74 Output Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V
Parameter
Description
Std. Units
tOCLKQ
Clock-to-Q of the Output Data Register
1.00
ns
tOSUD
Data Setup Time for the Output Data Register
0.51
ns
tOHD
Data Hold Time for the Output Data Register
0.00
ns
tOCLR2Q
Asynchronous Clear-to-Q of the Output Data Register
1.34
ns
tOPRE2Q
Asynchronous Preset-to-Q of the Output Data Register
1.34
ns
tOREMCLR
Asynchronous Clear Removal Time for the Output Data Register
0.00
ns
tORECCLR
Asynchronous Clear Recovery Time for the Output Data Register
0.24
ns
tOREMPRE
Asynchronous Preset Removal Time for the Output Data Register
0.00
ns
tORECPRE
Asynchronous Preset Recovery Time for the Output Data Register
0.24
ns
tOWCLR
Asynchronous Clear Minimum Pulse Width for the Output Data Register
0.19
ns
tOWPRE
Asynchronous Preset Minimum Pulse Width for the Output Data Register
0.19
ns
tOCKMPWH
Clock Minimum Pulse Width HIGH for the Output Data Register
0.31
ns
tOCKMPWL
Clock Minimum Pulse Width LOW for the Output Data Register
0.28
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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