Revision 13 2-25 Table 2-25 Summary of I/O Timing Characteristics鈥擲oftware Default Settings " />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� AGLE600V5-FG256I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 100/166闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 1KB FLASH 600K 256-FBGA
妯欐簴鍖呰锛� 90
绯诲垪锛� IGLOOe
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 13824
RAM 浣嶇附瑷堬細 110592
杓稿叆/杓稿嚭鏁�(sh霉)锛� 165
闁€鏁�(sh霉)锛� 600000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 256-LBGA
渚涙噳鍟嗚ō鍌欏皝瑁濓細 256-FPBGA锛�17x17锛�
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�绗�90闋�绗�91闋�绗�92闋�绗�93闋�绗�94闋�绗�95闋�绗�96闋�绗�97闋�绗�98闋�绗�99闋�鐣跺墠绗�100闋�绗�101闋�绗�102闋�绗�103闋�绗�104闋�绗�105闋�绗�106闋�绗�107闋�绗�108闋�绗�109闋�绗�110闋�绗�111闋�绗�112闋�绗�113闋�绗�114闋�绗�115闋�绗�116闋�绗�117闋�绗�118闋�绗�119闋�绗�120闋�绗�121闋�绗�122闋�绗�123闋�绗�124闋�绗�125闋�绗�126闋�绗�127闋�绗�128闋�绗�129闋�绗�130闋�绗�131闋�绗�132闋�绗�133闋�绗�134闋�绗�135闋�绗�136闋�绗�137闋�绗�138闋�绗�139闋�绗�140闋�绗�141闋�绗�142闋�绗�143闋�绗�144闋�绗�145闋�绗�146闋�绗�147闋�绗�148闋�绗�149闋�绗�150闋�绗�151闋�绗�152闋�绗�153闋�绗�154闋�绗�155闋�绗�156闋�绗�157闋�绗�158闋�绗�159闋�绗�160闋�绗�161闋�绗�162闋�绗�163闋�绗�164闋�绗�165闋�绗�166闋�
IGLOOe Low Power Flash FPGAs
Revision 13
2-25
Table 2-25 Summary of I/O Timing Characteristics鈥擲oftware Default Settings
Std. Speed Grade, Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI (per standard)
I/O Standard
D
rive
S
tre
ng
th
(mA)
Eq
ui
va
le
nt
Sof
twar
eDefau
lt
D
rive
S
tre
ng
th
Op
tio
n
1 (m
A)
Slew
Rate
C
ap
a
citive
L
o
a
d
(pF
)
Ex
tern
al
Re
sistor
(
)
t DO
U
T
(ns)
t DP
(ns)
t DI
N
(ns)
t PY
(ns)
t PYS
(ns)
t EOUT
(ns)
t ZL
(ns)
t ZH
(ns)
t LZ
(ns)
t HZ
(ns)
t ZL
S
(ns)
t ZH
S
(n
s)
Un
it
s
3.3 V LVTTL /
3.3 V LVCMOS
12
High 5
鈥�
0.97 2.12 0.18 1.08 1.34 0.66 2.17 1.69 2.71 3.08 5.76 5.28 ns
3.3 V LVCMOS
Wide Range1, 2
100 A
12
High
5
鈥�
0.972.960.181.421.840.662.982.283.864.366.585.87 ns
2.5 V LVCMOS
12
High
5
鈥�
.097 2.15 0.18 1.31 1.41 0.66 2.20 1.85 2.78 2.98 5.80 5.45 ns
1.8 V LVCMOS
12
High 5
鈥�
0.97 2.37 0.18 1.27 1.59 0.66 2.42 2.03 3.07 3.57 6.02 5.62 ns
1.5 V LVCMOS
12
High 5
鈥�
0.97 2.69 0.18 1.47 1.77 0.66 2.75 2.30 3.24 3.67 6.35 5.89 ns
3.3 V PCI
Per
PCI
spec
鈥�
High 10 25 3 0.97 2.38 0.18 0.96 1.42 0.66 2.43 1.80 2.72 3.08 6.03 5.39 ns
3.3 V PCI-X
Per
PCI-X
spec
鈥�
High 10 25 3 0.97 2.38 0.19 0.92 1.34 0.66 2.43 1.80 2.72 3.08 6.03 5.39 ns
3.3 V GTL
204
鈥�
High 10
25 0.97 1.78 0.19 2.35
鈥�
0.66 1.80 1.78
鈥�
5.39 5.38 ns
2.5 V GTL
204
鈥�
High 10
25 0.97 1.85 0.19 1.98
鈥�
0.66 1.89 1.82
鈥�
5.49 5.42 ns
3.3 V GTL+
35
鈥�
High 10
25 0.97 1.80 0.19 1.32
鈥�
0.66 1.84 1.77
鈥�
5.44 5.36 ns
2.5 V GTL+
33
鈥�
High 10
25 0.97 1.92 0.19 1.26
鈥�
0.66 1.96 1.80
鈥�
5.56 5.40 ns
HSTL (I)
8
鈥�
High 20
50 0.97 2.67 0.18 1.72
鈥�
0.66 2.72 2.67
鈥�
6.32 6.26 ns
HSTL (II)
15
鈥�
High 20
25 0.97 2.55 0.18 1.72
鈥�
0.66 2.60 2.34
鈥�
6.20 5.93 ns
SSTL2 (I)
15
鈥�
High 30
50 0.97 1.86 0.19 1.12
鈥�
0.66 1.90 1.68
鈥�
5.50 5.28 ns
SSTL2 (II)
18
鈥�
High 30
25 0.97 1.89 0.19 1.12
鈥�
0.66 1.93 1.62
鈥�
5.53 5.22 ns
SSTL3 (I)
14
鈥�
High 30
50 0.97 2.00 0.19 1.06
鈥�
0.66 2.04 1.67
鈥�
5.64 5.27 ns
SSTL3 (II)
21
鈥�
High 30
25 0.97 1.81 0.19 1.06
鈥�
0.66 1.85 1.55
鈥�
5.45 5.14 ns
LVDS
24
鈥�
High
鈥�
鈥� 0.97 1.73 0.19 1.62
鈥撯€撯€撯€撯€撯€�
鈥撯€�
ns
LVPECL
24
鈥�
High
鈥�
鈥� 0.97 1.65 0.18 1.42
鈥撯€撯€撯€撯€撯€�
鈥撯€�
ns
Notes:
1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is
卤100 A. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the
IBIS models.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
3. Resistance is used to measure I/O propagation delays as defined in PCI Specifications. See Figure 2-12 on page 2-49 for
connectivity. This resistor is not required during normal operation.
4. Output drive strength is below JEDEC specification.
5. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
鐩搁棞PDF璩囨枡
PDF鎻忚堪
EPF10K50VQC240-3 IC FLEX 10KA FPGA 50K 240-PQFP
EPF10K50VBC356-4N IC FLEX 10KV FPGA 50K 356-BGA
EPF10K50VBC356-4 IC FLEX 10KV FPGA 50K 356-BGA
A54SX16P-2TQG144I IC FPGA SX 24K GATES 144-TQFP
A54SX16P-2TQ144I IC FPGA SX 24K GATES 144-TQFP
鐩搁棞浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
AGLE600V5-FG484 鍔熻兘鎻忚堪:IC FPGA 1KB FLASH 600K 484-FBGA RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:IGLOOe 妯欐簴鍖呰:40 绯诲垪:SX-A LAB/CLB鏁�(sh霉):6036 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�:- 杓稿叆/杓稿嚭鏁�(sh霉):360 闁€鏁�(sh霉):108000 闆绘簮闆诲:2.25 V ~ 5.25 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 70°C 灏佽/澶栨:484-BGA 渚涙噳鍟嗚ō鍌欏皝瑁�:484-FPBGA锛�27X27锛�
AGLE600V5-FG484I 鍔熻兘鎻忚堪:IC FPGA 1KB FLASH 600K 484-FBGA RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:IGLOOe 鐢�(ch菐n)鍝佸煿瑷撴ā濉�:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 鐗硅壊鐢�(ch菐n)鍝�:Cyclone? IV FPGAs 妯欐簴鍖呰:60 绯诲垪:CYCLONE® IV GX LAB/CLB鏁�(sh霉):9360 閭忚集鍏冧欢/鍠厓鏁�(sh霉):149760 RAM 浣嶇附瑷�:6635520 杓稿叆/杓稿嚭鏁�(sh霉):270 闁€鏁�(sh霉):- 闆绘簮闆诲:1.16 V ~ 1.24 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 85°C 灏佽/澶栨:484-BGA 渚涙噳鍟嗚ō鍌欏皝瑁�:484-FBGA锛�23x23锛�
AGLE600V5-FG896 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE600V5-FG896ES 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE600V5-FG896I 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology