2-90 Revision 13 1.2 V DC Core Voltage Table 2-141 AGLE600 Global Resource
參數(shù)資料
型號： AGLE600V2-FG484
廠商： Microsemi SoC
文件頁數(shù)： 7/166頁
文件大?。?/td> 0K
描述： IC FPGA 1KB FLASH 600K 484-FBGA
標(biāo)準(zhǔn)包裝： 60
系列： IGLOOe
邏輯元件/單元數(shù)： 13824
RAM 位總計： 110592
輸入/輸出數(shù)： 270
門數(shù)： 600000
電源電壓： 1.14 V ~ 1.575 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 70°C
封裝/外殼： 484-BGA
供應(yīng)商設(shè)備封裝： 484-FPBGA（23x23）
IGLOOe DC and Switching Characteristics
2-90
Revision 13
1.2 V DC Core Voltage
Table 2-141 AGLE600 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Parameter
Description
Std.
Units
Min.1
Max.2
tRCKL
Input Low Delay for Global Clock
2.22
2.67
ns
tRCKH
Input High Delay for Global Clock
2.32
2.93
ns
tRCKMPWH
Minimum Pulse Width HIGH for Global Clock
1.40
ns
tRCKMPWL
Minimum Pulse Width LOW for Global Clock
1.65
ns
tRCKSW
Maximum Skew for Global Clock
0.61
ns
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.
Table 2-142 AGLE3000 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Parameter
Description
Std.
Units
Min.1
Max.2
tRCKL
Input Low Delay for Global Clock
2.83
3.27
ns
tRCKH
Input High Delay for Global Clock
3.00
3.61
ns
tRCKMPWH
Minimum Pulse Width HIGH for Global Clock
1.40
ns
tRCKMPWL
Minimum Pulse Width LOW for Global Clock
1.65
ns
tRCKSW
Maximum Skew for Global Clock
0.61
ns
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.
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參數(shù)描述
AGLE600V2-FG484I 功能描述:IC FPGA 1KB FLASH 600K 484-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:IGLOOe 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
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