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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | AGLE600V2-FG484 |
| 寤犲晢锛� | Microsemi SoC |
| 鏂囦欢闋佹暩(sh霉)锛� | 26/166闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC FPGA 1KB FLASH 600K 484-FBGA |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 60 |
| 绯诲垪锛� | IGLOOe |
| 閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� | 13824 |
| RAM 浣嶇附瑷�(j矛)锛� | 110592 |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 270 |
| 闁€鏁�(sh霉)锛� | 600000 |
| 闆绘簮闆诲锛� | 1.14 V ~ 1.575 V |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 灏佽/澶栨锛� | 484-BGA |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 484-FPBGA锛�23x23锛� |
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IGLOOe Low Power Flash FPGAs
Revision 13
2-107
Applies to 1.2 V DC Core Voltage
Table 2-150 FIFO
Commercial-Case Conditions: TJ = 70掳C, VCC = 1.14 V
Parameter
Description
Std.
Units
tENS
REN, WEN Setup Time
4.13
ns
tENH
REN, WEN Hold Time
0.31
ns
tBKS
BLK Setup Time
0.47
ns
tBKH
BLK Hold Time
0.00
ns
tDS
Input Data (WD) Setup Time
1.56
ns
tDH
Input Data (WD) Hold Time
0.49
ns
tCKQ1
Clock HIGH to New Data Valid on RD (pass-through)
6.80
ns
tCKQ2
Clock HIGH to New Data Valid on RD (pipelined)
3.62
ns
tRCKEF
RCLK HIGH to Empty Flag Valid
7.23
ns
tWCKFF
WCLK HIGH to Full Flag Valid
6.85
ns
tCKAF
Clock HIGH to Almost Empty/Full Flag Valid
26.61
ns
tRSTFG
RESET LOW to Empty/Full Flag Valid
7.12
ns
tRSTAF
RESET LOW to Almost Empty/Full Flag Valid
26.33
ns
tRSTBQ
RESET LOW to Data Out LOW on RD (pass-through)
4.09
ns
RESET LOW to Data Out LOW on RD (pipelined)
4.09
ns
tREMRSTB
RESET Removal
1.23
ns
tRECRSTB
RESET Recovery
6.58
ns
tMPWRSTB
RESET Minimum Pulse Width
1.18
ns
tCYC
Clock Cycle Time
10.90
ns
FMAX
Maximum Frequency
92
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating values.
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
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| AGLE600V2-FG484I | 鍔熻兘鎻忚堪:IC FPGA 1KB FLASH 600K 484-FBGA RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪锛� 绯诲垪:IGLOOe 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 鐗硅壊鐢�(ch菐n)鍝�:Cyclone? IV FPGAs 妯�(bi膩o)婧�(zh菙n)鍖呰:60 绯诲垪:CYCLONE® IV GX LAB/CLB鏁�(sh霉):9360 閭忚集鍏冧欢/鍠厓鏁�(sh霉):149760 RAM 浣嶇附瑷�(j矛):6635520 杓稿叆/杓稿嚭鏁�(sh霉):270 闁€鏁�(sh霉):- 闆绘簮闆诲:1.16 V ~ 1.24 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 85°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FBGA锛�23x23锛� |
| AGLE600V2-FG896 | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology |
| AGLE600V2-FG896ES | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology |
| AGLE600V2-FG896I | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology |
| AGLE600V2-FG896PP | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology |
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