1-2 Revision 23 Flash Advantages Low Power Flash-based IGLOO devices exhibit power characteristics similar to " />
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IGLOO Device Family Overview
1-2
Revision 23
Flash Advantages
Low Power
Flash-based IGLOO devices exhibit power characteristics similar to those of an ASIC, making them an
ideal choice for power-sensitive applications. IGLOO devices have only a very limited power-on current
surge and no high-current transition period, both of which occur on many FPGAs.
IGLOO devices also have low dynamic power consumption to further maximize power savings; power is
even further reduced by the use of a 1.2 V core voltage.
Low dynamic power consumption, combined with low static power consumption and Flash*Freeze
technology, gives the IGLOO device the lowest total system power offered by any FPGA.
Security
Nonvolatile, flash-based IGLOO devices do not require a boot PROM, so there is no vulnerable external
bitstream that can be easily copied. IGLOO devices incorporate FlashLock, which provides a unique
combination of reprogrammability and design security without external overhead, advantages that only
an FPGA with nonvolatile flash programming can offer.
IGLOO devices utilize a 128-bit flash-based lock and a separate AES key to provide the highest level of
protection in the FPGA industry for intellectual property and configuration data. In addition, all FlashROM
data in IGLOO devices can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192)
bit block cipher encryption standard. AES was adopted by the National Institute of Standards and
Technology (NIST) in 2000 and replaces the 1977 DES standard. IGLOO devices have a built-in AES
decryption engine and a flash-based AES key that make them the most comprehensive programmable
logic device security solution available today. IGLOO devices with AES-based security provide a high
level of protection for remote field updates over public networks such as the Internet, and are designed to
ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP thieves.
Security, built into the FPGA fabric, is an inherent component of the IGLOO family. The flash cells are
located beneath seven metal layers, and many device design and layout techniques have been used to
make invasive attacks extremely difficult. The IGLOO family, with FlashLock and AES security, is unique
in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected with
industry-standard security, making remote ISP possible. An IGLOO device provides the best available
security for programmable logic designs.
Single Chip
Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the
configuration data is an inherent part of the FPGA structure, and no external configuration data needs to
be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based IGLOO FPGAs do
not require system configuration components such as EEPROMs or microcontrollers to load device
configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system
reliability.
Instant On
Flash-based IGLOO devices support Level 0 of the Instant On classification standard. This feature helps
in system component initialization, execution of critical tasks before the processor wakes up, setup and
configuration of memory blocks, clock generation, and bus activity management. The Instant On feature
of flash-based IGLOO devices greatly simplifies total system design and reduces total system cost, often
eliminating the need for CPLDs and clock generation PLLs. In addition, glitches and brownouts in system
power will not corrupt the IGLOO device's flash configuration, and unlike SRAM-based FPGAs, the
device will not have to be reloaded when system power is restored. This enables the reduction or
complete removal of the configuration PROM, expensive voltage monitor, brownout detection, and clock
generator devices from the PCB design. Flash-based IGLOO devices simplify total system design and
reduce cost and design risk while increasing system reliability and improving system initialization time.
IGLOO flash FPGAs allow the user to quickly enter and exit Flash*Freeze mode. This is done almost
instantly (within 1 s) and the device retains configuration and data in registers and RAM. Unlike SRAM-
based FPGAs the device does not need to reload configuration and design state from external memory
components; instead it retains all necessary information to resume operation immediately.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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AGL125V2-FGG144 鍔熻兘鎻忚堪:IC FPGA IGLOO 1.2-1.5V 144FPBGA RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄e垪锛� 绯诲垪:IGLOO 妯�(bi膩o)婧�(zh菙n)鍖呰:24 绯诲垪:ECP2 LAB/CLB鏁�(sh霉):1500 閭忚集鍏冧欢/鍠厓鏁�(sh霉):12000 RAM 浣嶇附瑷�(j矛):226304 杓稿叆/杓稿嚭鏁�(sh霉):131 闁€鏁�(sh霉):- 闆绘簮闆诲:1.14 V ~ 1.26 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 85°C 灏佽/澶栨:208-BFQFP 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:208-PQFP锛�28x28锛�
AGL125V2-FGG144I 鍔熻兘鎻忚堪:IC FPGA 1KB FLASH 125K 144FBGA RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄e垪锛� 绯诲垪:IGLOO 妯�(bi膩o)婧�(zh菙n)鍖呰:152 绯诲垪:IGLOO PLUS LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):792 RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):120 闁€鏁�(sh霉):30000 闆绘簮闆诲:1.14 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:289-TFBGA锛孋SBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:289-CSP锛�14x14锛�
AGL125V2-FGG144T 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:AGL125V2-FGG144T - Trays
AGL125V2-FQN144 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology