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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | AGL030V2-QNG48 |
| 寤犲晢锛� | Microsemi SoC |
| 鏂囦欢闋佹暩(sh霉)锛� | 34/250闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC FPGA 1KB FLASH 30K 48-QFN |
| 妯欐簴鍖呰锛� | 260 |
| 绯诲垪锛� | IGLOO |
| 閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� | 768 |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 34 |
| 闁€鏁�(sh霉)锛� | 30000 |
| 闆绘簮闆诲锛� | 1.14 V ~ 1.575 V |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 灏佽/澶栨锛� | 48-VFQFN 瑁搁湶鐒婄洡 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 48-QFN锛�6x6锛� |
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IGLOO Low Power Flash FPGAs
Revision 23
2-113
Clock Conditioning Circuits
CCC Electrical Specifications
Timing Characteristics
Table 2-189 IGLOO CCC/PLL Specification
For IGLOO V2 or V5 Devices, 1.5 V DC Core Supply Voltage
Parameter
Min.
Typ.
Max.
Units
Clock Conditioning Circuitry Input Frequency fIN_CCC
1.5
250
MHz
Clock Conditioning Circuitry Output Frequency fOUT_CCC
0.75
250
MHz
Delay Increments in Programmable Delay Blocks 1, 2
3603
ps
Number of Programmable Values in Each Programmable Delay Block
32
Serial Clock (SCLK) for Dynamic PLL4, 5
100
ns
Input Cycle-to-Cycle Jitter (peak magnitude)
1
ns
Acquisition Time
LockControl = 0
300
s
LockControl = 1
6.0
ms
Tracking Jitter6
LockControl = 0
2.5
ns
LockControl = 1
1.5
ns
Output Duty Cycle
48.5
51.5
%
Delay Range in Block: Programmable Delay 1 1, 2
1.25
15.65
ns
Delay Range in Block: Programmable Delay 2 1, 2
0.469
15.65
ns
Delay Range in Block: Fixed Delay 1, 2
3.5
ns
CCC Output Peak-to-Peak Period Jitter FCCC_OUT
Maximum Peak-to-Peak Jitter Data7
SSO
48 SSO 88 SSO 168
0.75 MHz to 50 MHz
0.60%
0.80%
1.20%
50 MHz to 160 MHz
4.00%
6.00%
12.00%
Notes:
1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-7 and Table 2-7 on page 2-7 for deratings.
2. TJ = 25掳C, VCC = 1.5 V
3. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay
increments are available. Refer to the Libero SoC Online Help associated with the core for more information.
4. The AGL030 device does not support a PLL.
5. Maximum value obtained for a Std. speed grade device in Worst-Case Commercial Conditions. For specific junction
temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
6. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock edge.
Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter parameter.
7. Measurements done with LVTTL 3.3 V, 8 mA I/O drive strength, and high slew Rate. VCC/VCCPLL = 1.14 V, VQ/PQ/TQ type of
packages, 20 pF load.
8. Simultaneously Switching Outputs (SSOs) are outputs that are synchronous to a single clock domain and have clock-to-out
times that are within 卤200 ps of each other. Switching I/Os are placed outside of the PLL bank. Refer to the "Simultaneously
Switching Outputs (SSOs) and Printed Circuit Board Layout" section in the IGLOO FPGA Fabric User鈥檚 Guide.
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