2-40 Revision 23 The length of time an I/O can withstand IOSH
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鍨嬭櫉(h脿o)锛� AGL030V2-QNG48
寤犲晢锛� Microsemi SoC
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鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA 1KB FLASH 30K 48-QFN
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绯诲垪锛� IGLOO
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杓稿叆/杓稿嚭鏁�(sh霉)锛� 34
闁€鏁�(sh霉)锛� 30000
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瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
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IGLOO DC and Switching Characteristics
2-40
Revision 23
The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The
reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of
analysis.
For example, at 100掳C, the short current condition would have to be sustained for more than six months
to cause a reliability concern. The I/O design does not contain any short circuit protection, but such
protection would only be needed in extremely prolonged stress conditions.
Table 2-44 I/O Short Currents IOSH/IOSL
Applicable to Standard I/O Banks
Drive Strength
IOSL (mA)*
IOSH (mA)*
3.3 V LVTTL / 3.3 V LVCMOS
2 mA
25
27
4 mA
25
27
6 mA
51
54
8 mA
51
54
3.3 V LVCMOS Wide Range
100
A
Same as regular 3.3 V LVCMOS Same as regular 3.3 V LVCMOS
2.5 V LVCMOS
2 mA
16
18
4 mA
16
18
6 mA
32
37
8 mA
32
37
1.8 V LVCMOS
2 mA
9
11
4 mA
17
22
1.5 V LVCMOS
2 mA
13
16
1.2 V LVCMOS
1 mA
20
26
1.2 V LVCMOS Wide Range
100
A20
26
Note: *TJ = 100掳C
Table 2-45 Duration of Short Circuit Event before Failure
Temperature
Time before Failure
鈥�40掳C
> 20 years
鈥�20掳C
> 20 years
0掳C
> 20 years
25掳C
> 20 years
70掳C
5 years
85掳C
2 years
100掳C
6 months
Table 2-46 I/O Input Rise Time, Fall Time, and Related I/O Reliability1
Input Buffer
Input Rise/Fall Time
(min.)
Input Rise/Fall Time
(max.)
Reliability
LVTTL/LVCMOS
No requirement
10 ns *
20 years (100掳C)
LVDS/B-LVDS/M-LVDS/
LVPECL
No requirement
10 ns *
10 years (100掳C)
Note: The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the
noise is low, then the rise time and fall time of input buffers can be increased beyond the
maximum value. The longer the rise/fall times, the more susceptible the input signal is to the
board noise. Microsemi recommends signal integrity evaluation/characterization of the system to
ensure that there is no excessive noise coupling into input signals.
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