Revision 4 2-219 Input Register Timing Characteristics Figure 2-139 Input Register Timin" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� AFS250-2FGG256I
寤犲晢锛� Microsemi SoC
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 152/334闋�(y猫)
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA 2MB FLASH 250K 256FBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 90
绯诲垪锛� Fusion®
RAM 浣嶇附瑷�(j矛)锛� 36864
杓稿叆/杓稿嚭鏁�(sh霉)锛� 114
闁€鏁�(sh霉)锛� 250000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 100°C
灏佽/澶栨锛� 256-LBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 256-FPBGA锛�17x17锛�
绗�1闋�(y猫)绗�2闋�(y猫)绗�3闋�(y猫)绗�4闋�(y猫)绗�5闋�(y猫)绗�6闋�(y猫)绗�7闋�(y猫)绗�8闋�(y猫)绗�9闋�(y猫)绗�10闋�(y猫)绗�11闋�(y猫)绗�12闋�(y猫)绗�13闋�(y猫)绗�14闋�(y猫)绗�15闋�(y猫)绗�16闋�(y猫)绗�17闋�(y猫)绗�18闋�(y猫)绗�19闋�(y猫)绗�20闋�(y猫)绗�21闋�(y猫)绗�22闋�(y猫)绗�23闋�(y猫)绗�24闋�(y猫)绗�25闋�(y猫)绗�26闋�(y猫)绗�27闋�(y猫)绗�28闋�(y猫)绗�29闋�(y猫)绗�30闋�(y猫)绗�31闋�(y猫)绗�32闋�(y猫)绗�33闋�(y猫)绗�34闋�(y猫)绗�35闋�(y猫)绗�36闋�(y猫)绗�37闋�(y猫)绗�38闋�(y猫)绗�39闋�(y猫)绗�40闋�(y猫)绗�41闋�(y猫)绗�42闋�(y猫)绗�43闋�(y猫)绗�44闋�(y猫)绗�45闋�(y猫)绗�46闋�(y猫)绗�47闋�(y猫)绗�48闋�(y猫)绗�49闋�(y猫)绗�50闋�(y猫)绗�51闋�(y猫)绗�52闋�(y猫)绗�53闋�(y猫)绗�54闋�(y猫)绗�55闋�(y猫)绗�56闋�(y猫)绗�57闋�(y猫)绗�58闋�(y猫)绗�59闋�(y猫)绗�60闋�(y猫)绗�61闋�(y猫)绗�62闋�(y猫)绗�63闋�(y猫)绗�64闋�(y猫)绗�65闋�(y猫)绗�66闋�(y猫)绗�67闋�(y猫)绗�68闋�(y猫)绗�69闋�(y猫)绗�70闋�(y猫)绗�71闋�(y猫)绗�72闋�(y猫)绗�73闋�(y猫)绗�74闋�(y猫)绗�75闋�(y猫)绗�76闋�(y猫)绗�77闋�(y猫)绗�78闋�(y猫)绗�79闋�(y猫)绗�80闋�(y猫)绗�81闋�(y猫)绗�82闋�(y猫)绗�83闋�(y猫)绗�84闋�(y猫)绗�85闋�(y猫)绗�86闋�(y猫)绗�87闋�(y猫)绗�88闋�(y猫)绗�89闋�(y猫)绗�90闋�(y猫)绗�91闋�(y猫)绗�92闋�(y猫)绗�93闋�(y猫)绗�94闋�(y猫)绗�95闋�(y猫)绗�96闋�(y猫)绗�97闋�(y猫)绗�98闋�(y猫)绗�99闋�(y猫)绗�100闋�(y猫)绗�101闋�(y猫)绗�102闋�(y猫)绗�103闋�(y猫)绗�104闋�(y猫)绗�105闋�(y猫)绗�106闋�(y猫)绗�107闋�(y猫)绗�108闋�(y猫)绗�109闋�(y猫)绗�110闋�(y猫)绗�111闋�(y猫)绗�112闋�(y猫)绗�113闋�(y猫)绗�114闋�(y猫)绗�115闋�(y猫)绗�116闋�(y猫)绗�117闋�(y猫)绗�118闋�(y猫)绗�119闋�(y猫)绗�120闋�(y猫)绗�121闋�(y猫)绗�122闋�(y猫)绗�123闋�(y猫)绗�124闋�(y猫)绗�125闋�(y猫)绗�126闋�(y猫)绗�127闋�(y猫)绗�128闋�(y猫)绗�129闋�(y猫)绗�130闋�(y猫)绗�131闋�(y猫)绗�132闋�(y猫)绗�133闋�(y猫)绗�134闋�(y猫)绗�135闋�(y猫)绗�136闋�(y猫)绗�137闋�(y猫)绗�138闋�(y猫)绗�139闋�(y猫)绗�140闋�(y猫)绗�141闋�(y猫)绗�142闋�(y猫)绗�143闋�(y猫)绗�144闋�(y猫)绗�145闋�(y猫)绗�146闋�(y猫)绗�147闋�(y猫)绗�148闋�(y猫)绗�149闋�(y猫)绗�150闋�(y猫)绗�151闋�(y猫)鐣�(d膩ng)鍓嶇152闋�(y猫)绗�153闋�(y猫)绗�154闋�(y猫)绗�155闋�(y猫)绗�156闋�(y猫)绗�157闋�(y猫)绗�158闋�(y猫)绗�159闋�(y猫)绗�160闋�(y猫)绗�161闋�(y猫)绗�162闋�(y猫)绗�163闋�(y猫)绗�164闋�(y猫)绗�165闋�(y猫)绗�166闋�(y猫)绗�167闋�(y猫)绗�168闋�(y猫)绗�169闋�(y猫)绗�170闋�(y猫)绗�171闋�(y猫)绗�172闋�(y猫)绗�173闋�(y猫)绗�174闋�(y猫)绗�175闋�(y猫)绗�176闋�(y猫)绗�177闋�(y猫)绗�178闋�(y猫)绗�179闋�(y猫)绗�180闋�(y猫)绗�181闋�(y猫)绗�182闋�(y猫)绗�183闋�(y猫)绗�184闋�(y猫)绗�185闋�(y猫)绗�186闋�(y猫)绗�187闋�(y猫)绗�188闋�(y猫)绗�189闋�(y猫)绗�190闋�(y猫)绗�191闋�(y猫)绗�192闋�(y猫)绗�193闋�(y猫)绗�194闋�(y猫)绗�195闋�(y猫)绗�196闋�(y猫)绗�197闋�(y猫)绗�198闋�(y猫)绗�199闋�(y猫)绗�200闋�(y猫)绗�201闋�(y猫)绗�202闋�(y猫)绗�203闋�(y猫)绗�204闋�(y猫)绗�205闋�(y猫)绗�206闋�(y猫)绗�207闋�(y猫)绗�208闋�(y猫)绗�209闋�(y猫)绗�210闋�(y猫)绗�211闋�(y猫)绗�212闋�(y猫)绗�213闋�(y猫)绗�214闋�(y猫)绗�215闋�(y猫)绗�216闋�(y猫)绗�217闋�(y猫)绗�218闋�(y猫)绗�219闋�(y猫)绗�220闋�(y猫)绗�221闋�(y猫)绗�222闋�(y猫)绗�223闋�(y猫)绗�224闋�(y猫)绗�225闋�(y猫)绗�226闋�(y猫)绗�227闋�(y猫)绗�228闋�(y猫)绗�229闋�(y猫)绗�230闋�(y猫)绗�231闋�(y猫)绗�232闋�(y猫)绗�233闋�(y猫)绗�234闋�(y猫)绗�235闋�(y猫)绗�236闋�(y猫)绗�237闋�(y猫)绗�238闋�(y猫)绗�239闋�(y猫)绗�240闋�(y猫)绗�241闋�(y猫)绗�242闋�(y猫)绗�243闋�(y猫)绗�244闋�(y猫)绗�245闋�(y猫)绗�246闋�(y猫)绗�247闋�(y猫)绗�248闋�(y猫)绗�249闋�(y猫)绗�250闋�(y猫)绗�251闋�(y猫)绗�252闋�(y猫)绗�253闋�(y猫)绗�254闋�(y猫)绗�255闋�(y猫)绗�256闋�(y猫)绗�257闋�(y猫)绗�258闋�(y猫)绗�259闋�(y猫)绗�260闋�(y猫)绗�261闋�(y猫)绗�262闋�(y猫)绗�263闋�(y猫)绗�264闋�(y猫)绗�265闋�(y猫)绗�266闋�(y猫)绗�267闋�(y猫)绗�268闋�(y猫)绗�269闋�(y猫)绗�270闋�(y猫)绗�271闋�(y猫)绗�272闋�(y猫)绗�273闋�(y猫)绗�274闋�(y猫)绗�275闋�(y猫)绗�276闋�(y猫)绗�277闋�(y猫)绗�278闋�(y猫)绗�279闋�(y猫)绗�280闋�(y猫)绗�281闋�(y猫)绗�282闋�(y猫)绗�283闋�(y猫)绗�284闋�(y猫)绗�285闋�(y猫)绗�286闋�(y猫)绗�287闋�(y猫)绗�288闋�(y猫)绗�289闋�(y猫)绗�290闋�(y猫)绗�291闋�(y猫)绗�292闋�(y猫)绗�293闋�(y猫)绗�294闋�(y猫)绗�295闋�(y猫)绗�296闋�(y猫)绗�297闋�(y猫)绗�298闋�(y猫)绗�299闋�(y猫)绗�300闋�(y猫)绗�301闋�(y猫)绗�302闋�(y猫)绗�303闋�(y猫)绗�304闋�(y猫)绗�305闋�(y猫)绗�306闋�(y猫)绗�307闋�(y猫)绗�308闋�(y猫)绗�309闋�(y猫)绗�310闋�(y猫)绗�311闋�(y猫)绗�312闋�(y猫)绗�313闋�(y猫)绗�314闋�(y猫)绗�315闋�(y猫)绗�316闋�(y猫)绗�317闋�(y猫)绗�318闋�(y猫)绗�319闋�(y猫)绗�320闋�(y猫)绗�321闋�(y猫)绗�322闋�(y猫)绗�323闋�(y猫)绗�324闋�(y猫)绗�325闋�(y猫)绗�326闋�(y猫)绗�327闋�(y猫)绗�328闋�(y猫)绗�329闋�(y猫)绗�330闋�(y猫)绗�331闋�(y猫)绗�332闋�(y猫)绗�333闋�(y猫)绗�334闋�(y猫)
Fusion Family of Mixed Signal FPGAs
Revision 4
2-219
Input Register
Timing Characteristics
Figure 2-139 Input Register Timing Diagram
50%
Preset
Clear
Out_1
CLK
Data
Enable
tISUE
50%
tISUD
tIHD
50%
tICLKQ
1
0
tIHE
tIRECPRE
tIREMPRE
tIRECCLR
tIREMCLR
tIWCLR
tIWPRE
tIPRE2Q
tICLR2Q
tICKMPWH tICKMPWL
50%
Table 2-176 Input Data Register Propagation Delays
Commercial Temperature Range Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V
Parameter
Description
鈥�2
鈥�1
Std.
Units
tICLKQ
Clock-to-Q of the Input Data Register
0.24
0.27
0.32
ns
tISUD
Data Setup Time for the Input Data Register
0.26
0.30
0.35
ns
tIHD
Data Hold Time for the Input Data Register
0.00
ns
tISUE
Enable Setup Time for the Input Data Register
0.37
0.42
0.50
ns
tIHE
Enable Hold Time for the Input Data Register
0.00
ns
tICLR2Q
Asynchronous Clear-to-Q of the Input Data Register
0.45
0.52
0.61
ns
tIPRE2Q
Asynchronous Preset-to-Q of the Input Data Register
0.45
0.52
0.61
ns
tIREMCLR
Asynchronous Clear Removal Time for the Input Data Register
0.00
ns
tIRECCLR
Asynchronous Clear Recovery Time for the Input Data Register
0.22
0.25
0.30
ns
tIREMPRE
Asynchronous Preset Removal Time for the Input Data Register
0.00
ns
tIRECPRE
Asynchronous Preset Recovery Time for the Input Data Register
0.22
0.25
0.30
ns
tIWCLR
Asynchronous Clear Minimum Pulse Width for the Input Data Register
0.22
0.25
0.30
ns
tIWPRE
Asynchronous Preset Minimum Pulse Width for the Input Data Register
0.22
0.25
0.30
ns
tICKMPWH
Clock Minimum Pulse Width High for the Input Data Register
0.36
0.41
0.48
ns
tICKMPWL
Clock Minimum Pulse Width Low for the Input Data Register
0.32
0.37
0.43
ns
Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
983-009-010R031 BACKSHELL DB9 GREY PLASTIC
AYM40DRSS CONN EDGECARD 80POS DIP .156 SLD
ASM40DRSS CONN EDGECARD 80POS DIP .156 SLD
AGM40DRSS CONN EDGECARD 80POS DIP .156 SLD
ACC40DRYS-S93 CONN EDGECARD 80POS DIP .100 SLD
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
AFS250-2FGG256PP 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:Actel Fusion Mixed-Signal FPGAs
AFS250-2PQ208 鍔熻兘鎻忚堪:IC FPGA 2MB FLASH 250K 208PQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄e垪锛� 绯诲垪:Fusion® 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:256-FPBGA锛�17x17锛�
AFS250-2PQ208I 鍔熻兘鎻忚堪:IC FPGA 2MB FLASH 250K 208PQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄e垪锛� 绯诲垪:Fusion® 妯�(bi膩o)婧�(zh菙n)鍖呰:40 绯诲垪:SX-A LAB/CLB鏁�(sh霉):6036 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):360 闁€鏁�(sh霉):108000 闆绘簮闆诲:2.25 V ~ 5.25 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 70°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FPBGA锛�27X27锛�
AFS250-2PQ256ES 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:Actel Fusion Mixed-Signal FPGAs
AFS250-2PQ256I 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:Actel Fusion Mixed-Signal FPGAs