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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | AFS250-2FGG256I |
| 寤犲晢锛� | Microsemi SoC |
| 鏂囦欢闋佹暩(sh霉)锛� | 150/334闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC FPGA 2MB FLASH 250K 256FBGA |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 90 |
| 绯诲垪锛� | Fusion® |
| RAM 浣嶇附瑷�(j矛)锛� | 36864 |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 114 |
| 闁€鏁�(sh霉)锛� | 250000 |
| 闆绘簮闆诲锛� | 1.425 V ~ 1.575 V |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 宸ヤ綔婧害锛� | -40°C ~ 100°C |
| 灏佽/澶栨锛� | 256-LBGA |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 256-FPBGA锛�17x17锛� |
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Fusion Family of Mixed Signal FPGAs
Revision 4
2-217
Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear
Figure 2-138 Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear
Core
Array
Data Input I/O Register with
Active High Enable
Active High Clear
Positive Edge Triggered
Data Output Register and
Enable Output Register with
Active High Enable
Active High Clear
Positive Edge Triggered
Enable
CLK
Pad
Out
CLK
Enable
CLR
Data_out
Data
Y
AA
EOUT
DOUT
DQ
DFN1E1C1
E
CLR
DQ
DFN1E1C1
E
CLR
DQ
DFN1E1C1
E
CLR
D_Enable
BB
CC
DD
EE
FF
GG
LL
HH
JJ
KK
CLKBUF
INBUF
TRIBUF
INBUF
CLKBUF
INBUF
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| 983-009-010R031 | BACKSHELL DB9 GREY PLASTIC |
| AYM40DRSS | CONN EDGECARD 80POS DIP .156 SLD |
| ASM40DRSS | CONN EDGECARD 80POS DIP .156 SLD |
| AGM40DRSS | CONN EDGECARD 80POS DIP .156 SLD |
| ACC40DRYS-S93 | CONN EDGECARD 80POS DIP .100 SLD |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| AFS250-2FGG256PP | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:Actel Fusion Mixed-Signal FPGAs |
| AFS250-2PQ208 | 鍔熻兘鎻忚堪:IC FPGA 2MB FLASH 250K 208PQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪锛� 绯诲垪:Fusion® 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:256-FPBGA锛�17x17锛� |
| AFS250-2PQ208I | 鍔熻兘鎻忚堪:IC FPGA 2MB FLASH 250K 208PQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪锛� 绯诲垪:Fusion® 妯�(bi膩o)婧�(zh菙n)鍖呰:40 绯诲垪:SX-A LAB/CLB鏁�(sh霉):6036 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):360 闁€鏁�(sh霉):108000 闆绘簮闆诲:2.25 V ~ 5.25 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 70°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FPBGA锛�27X27锛� |
| AFS250-2PQ256ES | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:Actel Fusion Mixed-Signal FPGAs |
| AFS250-2PQ256I | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:Actel Fusion Mixed-Signal FPGAs |
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