2-72 Revision 4 The following signals are used to configure the FIFO4K18 memory element: WW and RW These signals enable" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� AFS090-2QNG180
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 322/334闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA 2MB FLASH 90K 180-QFN
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RAM 浣嶇附瑷堬細 27648
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灏佽/澶栨锛� 180-WFQFN
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 180-QFN锛�10x10锛�
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Device Architecture
2-72
Revision 4
The following signals are used to configure the FIFO4K18 memory element:
WW and RW
These signals enable the FIFO to be configured in one of the five allowable aspect ratios (Table 2-33).
WBLK and RBLK
These signals are active low and will enable the respective ports when Low. When the RBLK signal is
High, the corresponding port鈥檚 outputs hold the previous value.
WEN and REN
Read and write enables. WEN is active low and REN is active high by default. These signals can be
configured as active high or low.
WCLK and RCLK
These are the clock signals for the synchronous read and write operations. These can be driven
independently or with the same driver.
RPIPE
This signal is used to specify pipelined read on the output. A Low on RPIPE indicates a nonpipelined
read, and the data appears on the output in the same clock cycle. A High indicates a pipelined read, and
data appears on the output in the next clock cycle.
RESET
This active low signal resets the output to zero when asserted. It resets the FIFO counters. It also sets all
the RD pins Low, the FULL and AFULL pins Low, and the EMPTY and AEMPTY pins High (Table 2-34).
WD
This is the input data bus and is 18 bits wide. Not all 18 bits are valid in all configurations. When a data
width less than 18 is specified, unused higher-order signals must be grounded (Table 2-34).
RD
This is the output data bus and is 18 bits wide. Not all 18 bits are valid in all configurations. Like the WD
bus, high-order bits become unusable if the data width is less than 18. The output data on unused pins is
undefined (Table 2-34).
ESTOP, FSTOP
ESTOP is used to stop the FIFO read counter from further counting once the FIFO is empty (i.e., the
EMPTY flag goes High). A High on this signal inhibits the counting.
Table 2-33 Aspect Ratio Settings for WW[2:0]
WW2, WW1, WW0
RW2, RW1, RW0
D
W
000
4k脳1
001
2k脳2
010
1k脳4
011
512脳9
100
256脳18
101, 110, 111
Reserved
Table 2-34 Input Data Signal Usage for Different Aspect Ratios
D脳W
WD/RD Unused
4k
1
WD[17:1], RD[17:1]
2k
2
WD[17:2], RD[17:2]
1k
4
WD[17:4], RD[17:4]
512
9
WD[17:9], RD[17:9]
256
18
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