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參數(shù)資料
| 型號： | ADW71205WSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/20頁 |
| 文件大小： | 0K |
| 描述： | IC ADC RDC 12BIT W/OSC 44-LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 3 |
| 功率耗散（最大）： | 50mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LQFP |
| 供應(yīng)商設(shè)備封裝： | 44-LQFP（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個(gè)差分，單極 |
AD2S1205
Rev. A | Page 17 of 20
CIRCUIT DYNAMICS
LOOP RESPONSE MODEL
0
63
39
-01
1
ERROR
(ACCELERATION)
–
θIN
θOUT
VELOCITY
k1 × k2
1 – z–1
1 – bz–1
1 – z–1
c
1 – az–1
c
Sin/Cos LOOKUP
Figure 11. RDC System Response Block Diagram
The RDC is a mixed-signal device that uses two ADCs to
digitize signals from the resolver and a Type II tracking loop
to convert these to digital position and velocity words.
The first gain stage consists of the ADC gain on the Sin/Cos
inputs and the gain of the error signal into the first integrator.
The first integrator generates a signal proportional to velocity.
The compensation filter contains a pole and a zero that are used
to provide phase margin and reduce high frequency noise gain.
The second integrator is the same as the first and generates the
position output from the velocity signal. The Sin/Cos lookup has
unity gain. The values for each section are as follows:
ADC gain parameter (k1NOM = 1.8/2.5)
)
V
(
)
V
(
p
REF
IN
V
k2 =
(12)
Error gain parameter
π
×
=
2
10
18
6
k2
(13)
Compensator zero coefficient
4096
4095
=
a
(14)
Compensator pole coefficient
4096
4085
=
b
(15)
Integrator gain parameter
000
,
096
,
4
1
=
c
(16)
INT1 and INT2 transfer function
1
)
(
=
z
c
z
I
(17)
Compensation filter transfer function
1
)
(
=
bz
az
z
C
(18)
R2D open-loop transfer function
)
(
)
(
)
(
2
z
C
z
I
k2
k1
z
G
×
=
(19)
R2D closed-loop transfer function
)
(
1
)
(
)
(
z
G
z
G
z
H
+
=
(20)
The closed-loop magnitude and phase responses are that of a
To convert G(z) into the s-plane, an inverse bilinear transfor-
mation is performed by substituting the following equation
for z:
s
t
s
t
z
+
=
2
(21)
where t is the sampling period (1/4.096 MHz ≈ 244 ns).
Substitution yields the open-loop transfer function G(s).
)
1
(
2
)
1
(
1
)
1
(
2
)
1
(
1
4
1
)
1
(
)
(
2
b
t
s
a
t
s
t
s
st
b
a
k2
k1
s
G
+
×
+
+
×
+
×
+
×
×
=
(22)
This transformation produces the best matching at low frequencies
(f < fSAMPLE). At such frequencies (within the closed-loop bandwidth
of the AD2S1205), the transfer function can be simplified to
2
1
2
1
)
(
st
s
K
s
G
a
+
×
(23)
where:
b
a
k2
k1
K
b
t
a
t
a
×
=
+
=
+
=
)
1
(
)
1
(
2
)
1
(
)
1
(
2
)
1
(
2
1
Solving for each value gives t1 = 1 ms, t2 = 90 μs, and Ka ≈ 7.4 ×
106 s2. Note that the closed-loop response is described as
)
(
1
)
(
)
(
s
G
s
G
s
H
+
=
(24)
By converting the calculation to the s-domain, it is possible to
quantify the open-loop dc gain (Ka). This value is useful to
calculate the acceleration error of the loop (see the Sources of
Error section).
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