參數(shù)資料
型號(hào)： ADW71205WSTZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 20/20頁(yè)
文件大?。?/td> 0K
描述： IC ADC RDC 12BIT W/OSC 44-LQFP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 3
功率耗散（最大）： 50mW
電壓電源： 單電源
工作溫度： -40°C ~ 125°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 44-LQFP
供應(yīng)商設(shè)備封裝： 44-LQFP（10x10）
包裝： 托盤(pán)
輸入數(shù)目和類(lèi)型： 1 個(gè)差分，單極
AD2S1205
Rev. A | Page 9 of 20
THEORY OF OPERATION
The AD2S1205’s operation is based on a Type II tracking closed-
loop principle. The digitally implemented tracking loop continually
tracks the position and velocity of the resolver without the need
for external convert and wait states. As the resolver moves through
a position equivalent to the least significant bit weighting, the
tracking loop output is updated by 1 LSB.
The converter tracks the shaft angle (θ) by producing an output
angle () that is fed back and compared with the input angle
(θ); the difference between the two angles is the error, which is
driven towards 0 when the converter is correctly tracking the
input angle. To measure the error, S3 S1 is multiplied by Cos
and S2 S4 is multiplied by Sin to give
S4
S2
for
)
(
S1
S3
for
)
(
0
×
×
Sinφ
Cosθ
ωt
Sin
E
Cosφ
Sinθ
ωt
Sin
E
(2)
The difference is taken, giving
)
(
)
(
0
Sinφ
Cosθ
Cos
Sinθ
ωt
Sin
E
φ
×
(3)
This signal is demodulated using the internally generated
synthetic reference, yielding
)
(
0
φ
φ
Sin
Cosθ
Cos
Sinθ
E
(4)
Equation 4 is equivalent to E0Sin(θ ), which is approximately
equal to E0(θ ) for small values of θ , where θ is the
angular error.
The value E0(θ ) is the difference between the angular error
of the rotor and the digital angle output of the converter.
A phase-sensitive demodulator, some integrators, and a compen-
sation filter form a closed-loop system that seeks to null the
error signal. If this is accomplished, equals the resolver angle,
θ, within the rated accuracy of the converter. A Type II tracking
loop is used so that constant velocity inputs can be tracked
without inherent error.
For more information about the operation of the converter, see
the Circuit Dynamics section.
FAULT DETECTION CIRCUIT
The AD2S1205 fault detection circuit can sense loss of resolver
signals, out-of-range input signals, input signal mismatch, or
loss of position tracking; however, the position indicated by
the AD2S1205 may differ significantly from the actual shaft
position of the resolver.
MONITOR SIGNAL
The AD2S1205 generates a monitor signal by comparing the
angle in the position register to the incoming Sin and Cos signals
from the resolver. The monitor signal is created in a similar fashion
to the error signal (described in the Theory of Operation section).
The incoming Sinθ and Cosθ signals are multiplied by the Sin
and Cos of the output angle, respectively, and then these values
are added together:
)
(
)
(
Cosφ
Cosθ
A2
Sinφ
Sinθ
A1
Monitor
×
+
×
=
(5)
where:
A1 is the amplitude of the incoming Sin signal (A1 × Sinθ).
A2 is the amplitude of the incoming Cos signal (A2 × Cosθ).
θ is the resolver angle.
is the angle stored in the position register.
Note that Equation 5 is shown after demodulation with the
carrier signal Sin(ωt) removed. Also note that for a matched
input signal (that is, a no fault condition), A1 is equal to A2.
When A1 is equal to A2 and the converter is tracking
(therefore, θ is equal to ), the monitor signal output has a
constant magnitude of A1 (Monitor = A1 × (Sin2θ + Cos2θ) = A1),
which is independent of the shaft angle. When A1 does not
equal A2, the monitor signal magnitude alternates between A1
and A2 at twice the rate of the shaft rotation. The monitor
signal is used to detect degradation or loss of input signals.
LOSS OF SIGNAL DETECTION
Loss of signal (LOS) is detected when either resolver input (Sin
or Cos) falls below the specified LOS Sin/Cos threshold. The
AD2S1205 detects this by comparing the monitor signal to a
fixed minimum value. Without the use of external circuitry,
the AD2S1205 can detect the loss of up to three of the four
connections from the resolver. The addition of two external
68 kΩ resistors, as outlined in Figure 5, ensures that the loss of
all 4 connections, that is, complete removal of the resolver, may
also be detected. LOS is indicated by both DOS and LOT
latching as logic low outputs. The DOS and LOT pins are
reset to the no fault state by a rising edge of SAMPLE. The
LOS condition has priority over both the DOS and LOT
conditions, as shown in
. LOS is indicated within 57°
of the angular output error (worst case).
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