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| 型號： | ADV7604BBCZ-5P |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DIGITIZER VID/GRAPHIC 260BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Advantiv® |
| 類型： | 視頻數(shù)字轉(zhuǎn)換器 |
| 應(yīng)用： | HDTV |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 260-LFBGA，CSBGA |
| 供應(yīng)商設(shè)備封裝： | 260-CSPBGA（15x15） |
| 包裝： | 托盤 |
Data Sheet
ADV7604
Rev. D | Page 17 of 20
THEORY OF OPERATION
ANALOG FRONT END
The ADV7604 analogfront endcomprisesthree170 MHz, 12-bit
ADCs that digitize theanalog video signal beforeapplyingit to
the CP, enabling true 12-bit video decoding. The analog front
end uses differential channels to each ADC to ensurehigh
performance in a mixed-signal application.
The front end also includes a 12-channel input mux that enables
multiple video signals to be applied to the ADV7604 without
the requirement ofan external mux.
Three voltage clampcontrol loops ensurethat any dcoffsets are
removedfromthevideosignal.The voltageclamps arepositioned
in front ofeachADC toensurethat thevideosignal remainswithin
the range of the converter. Fine clamping of the videosignals is
performed downstream by digital fine clamping in the CP.
For component 525i, 625i, 525p, and 625p sources, 2× over-
sampling is performed. All other video standardsare 1×
oversampled. Oversampling the video signals reduces the
cost and complexity of external antialiasing filterswith the
benefit of an increased signal-to-noise ratio (SNR).
HDMI RECEIVER
The HDMIreceiver on the ADV7604 incorporates active
equalization of the HDMIdata signals. This equalization
compensates forthehighfrequency lossesinherent in HDMIand
DVIcabling, especiallyatlonger lengthsand higher frequencies.
The equalization is programmable. It is capable of equalizing
for cable lengthsup to 30 meters toachieverobust receiver
performance at even thehighest HDMIdata rates. The HDMI
receiver supports all HDTV formatsup to 1080p and all display
resolutions up to UXGA (1600 × 1200 at 60 Hz). The receiver
contains a programmable dataisland packet interrupt generator.
With the inclusionofHDCP, displayscan receiveencryptedvideo
content. The HDMIinterfaceoftheADV7604 allowsfor authen-
tication of a video receiver, decryption of encoded dataat the
receiver, and renewability of that authentication during trans-
mission as specified by the HDCP 1.3 protocol.
The HDMIreceiveroffersadvancedaudiofunctionality.It supports
multichannel I2S audio for up to eight channels. It also supports
a 6-DSD channel interface with each channel carrying an over-
sampled 1-bit representation of the audio signal as delivered on
a super audio CD (SACD). It incorporatesa DST interface that
outputs audio datadecoded from DST audio packets. The
ADV7604 can also receive HBR audio packet streams and
outputs them throughthe HBR interface in an SPDIF format
conforming to the IEC60958 standard. It supports multichannel
I2S audio for up to eight channels. The receiver also contains an
audio mute controller that can detect a variety of conditions
that may result in audible extraneous noisein the audio output.
On detection of these conditions, the audio data can be ramped
to prevent audio clicks or pops.
COMPONENT PROCESSOR (CP)
The CP section is capable of decoding/digitizing a wide range of
component videoformatsin any color space. Component video
standards supportedby the CP are 525i, 625i, 525p, 625p, 720p,
1080i, 1080p, 1250i, VGA up to UXGA at 60 Hz, and many
other standards.
The CP section of the ADV7604 contains an AGC block. In
cases where no embedded synchronization is present, the
video gain can be set manually. The AGC section is followed
by a digital clamp circuit that ensures that the video signal is
clamped to the correct blanking level. Automaticadjustments
within the CP include gain (contrast)and offset (brightness);
manual adjustment controls are also supported.
A fully programmable any-to-any 3 × 3 color space conversion
(CSC) matrix is placed between the analog frontend and the
CP section. This enables YPrPb-to-RGB and RGB-to-YCrCb
conversions. Many other standardsof color space can be
implemented using the color space converter.
The CP section contains circuitry to enable the detection of
Macrovision encodedYPrPb signals for 525i, 625i, 525p, and
625p. It is designed to be fully robust when decoding these
types of signals.
VBI extraction of CGMS data is performed by the CP section
of the ADV7604 for interlaced, progressive, and high definition
scanning rates. The data extracted can be read backover the I2C
interface.
CP PIXEL DATA OUTPUT MODES
The output section of the CP is highly flexible. It can be
configured in an SDR mode with one data packet perclock
cycle or in a DDR mode wheredata is presented on the rising
and falling edge of the clock. In SDR mode, a 16-/20-/24-bit
4:2:2 or 24-/30-/36-bit 4:4:4 output is possible. In these modes,
the HS, VS/FIELD, and DE/FIELD (where applicable)timing
referencesignals areprovided. In DDRmode, the ADV7604
can be configuredin an 8-/10-/12-bit 4:2:2 YCrCbor 12-bit 4:4:4
RGB/YCrCb pixel output interfacewith corresponding timing
signals.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7610 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Power, 165 MHz HDMI Receiver |
| ADV7610BBCZ | 功能描述:視頻 IC Single input HDMI Receiver with HDCP key RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| ADV7610BBCZ-P | 功能描述:視頻 IC Single input HDMI Receiver non HDCP key RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| ADV7610BBCZ-P-RL | 功能描述:視頻 IC Single input HDMI Receiver non HDCP key RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| ADV7610BBCZ-RL | 功能描述:視頻 IC Single input HDMI Receiver with HDCP key RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
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