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參數(shù)資料
| 型號： | ADV7604BBCZ-5P |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DIGITIZER VID/GRAPHIC 260BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Advantiv® |
| 類型： | 視頻數(shù)字轉(zhuǎn)換器 |
| 應(yīng)用： | HDTV |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 260-LFBGA，CSBGA |
| 供應(yīng)商設(shè)備封裝： | 260-CSPBGA（15x15） |
| 包裝： | 托盤 |
Data Sheet
ADV7604
Rev. D | Page 15 of 20
Pin No.
Mnemonic
Type
Description
R1
P12
Digital video output
Video Pixel Output Port.
R2
P13
Digital video output
Video Pixel Output Port.
R3
DGND
Ground
Ground.
R4
DGND
Ground
Ground.
R5
SCL
Digital I/O
I2C Port Serial Clock Input. Maximum clock rate of 400 kHz. SCL is the clock line
for the control port.
R6
DVDDIO
Power
Digital I/O Supply Voltage (3.3 V).
R7
INT1
Digital output
Interrupt Pin 1. Thispincanbe active loworactive high. Whenstatus bitschange,
this pin is triggered. The events that trigger an interrupt are underuser control.
R8
CLAMPIN
External clamp
External Clamp Signal. This is an optional mode of operationfor the ADV7604.
R9
DVDDIO
Power
Digital I/O Supply Voltage (3.3 V).
R10
DGND
Ground
Ground.
R11
FB_OUT
Misc digital
FB Output. This is the muxed fast blank output from TRI1 to TRI8
(programmable).
R12
SHARED_EDID
Digital input
EDID Flag. When high, allfour HDMI ports share common EDID. When low, Port D
does not share common EDID; Port D operates with a separate EDID.
R13
HS_IN1
Analog input
HS on Graphics Port 1. HS input signal is used in CP mode for 5-wire timing
mode. HS_IN1 is a 3.3 V input that is 5 V tolerant.
R14
AGND
Ground
Ground.
R15
Y_MUX_OUT
Analog output
Buffered Output of the Y Channel.
R16
TRI2
Analog input
Trilevel/bilevel input on the SCART or D-terminal connector. Results are
available via I2C. This signal can be buffered and output to the FB_OUT pin.
R17
AGND
Ground
Ground.
R18
AGND
Ground
Ground.
T1
P14
Digital video output
Video Pixel Output Port.
T2
P15
Digital video output
Video Pixel Output Port.
T3
DGND
Ground
Ground.
T4
DGND
Ground
Ground.
T5
P25
Digital video output
Video Pixel Output Port.
T6
DVDDIO
Power
Digital I/O Supply Voltage (3.3 V).
T7
SDA
Digital I/O
I2C Port Serial Data Input/Output Pin. SDA is the data line for the control port.
T8
SYNC_OUT/INT2
Digital output
Dual Purpose Pin. Sliced Synchronization Output Forthe CP Core.
Interrupt Pin 2. This pin canbe active low or activehigh. When statusbits change,
this pin is triggered. The events that trigger an interrupt are underuser control.
T9
DVDDIO
Power
Digital I/O Supply Voltage (3.3 V).
T10
DGND
Ground
Ground.
T11
RESET
Digital input
Chip Reset. Active low. Minimum low time for a reset to take place is 5 ms.
T12
AVLINK
Digital I/O
Digital SCART Control Channel.
T13
VS_IN1
Analog input
VS on Graphics Port 1. The VS input signal is used in CP mode for 5-wire timing
mode. VS_IN1 is a 3.3 V input that is 5 V tolerant.
T14
AGND
Ground
Ground.
T15
TRI1
Analog input
Trilevel/bilevel input on the SCART or D-terminal connector. Results are
available via I2C. This signal can be buffered and output to the FB_OUT pin.
T16
SYNC2
Analog input
Synchronization on greenor luma input (SOG/SOY). Used in embedded
synchronization mode. User configurable.
T17
AIN5
Analog video input
Analog Video Input Channel.
T18
AIN6
Analog video input
Analog Video Input Channel.
U1
P16
Digital video output
Video Pixel Output Port.
U2
P17
Digital video output
Video Pixel Output Port.
U3
P19
Digital video output
Video Pixel Output Port.
U4
P21
Digital video output
Video Pixel Output Port.
U5
P23
Digital video output
Video Pixel Output Port.
U6
DGND
Ground
Ground.
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