參數(shù)資料
型號(hào)： ADV7441ABSTZ-5P
廠商： Analog Devices Inc
文件頁數(shù)： 27/28頁
文件大小： 0K
描述： IC DECODER DIGITIZER 144LQFP
標(biāo)準(zhǔn)包裝： 1
系列： Advantiv®
類型： 視頻解碼器
應(yīng)用： HDTV，投影儀，機(jī)頂盒
安裝類型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-LQFP（20x20）
包裝： 托盤
ADV7441A
Data Sheet
Rev. H | Page 8 of 28
TIMING CHARACTERISTICS
AVDD = 1.71 V to 1.89 V, DVDD = 1.62 V to 1.98 V, DVDDIO = 2.97 V to 3.63 V, PVDD = 1.71 V to 1.89 V, TVDD = 3.135 V to 3.465 V,
CVDD = 1.71 V to 1.89 V. Operating temperature range is 40°C to +85°C, unless otherwise noted.
Table 4.
Parameter1, 2
Symbol
Test Conditions
Min
Typ
Max
Unit
SYSTEM CLOCK AND CRYSTAL
Crystal Nominal Frequency
28.6363
MHz
Crystal Frequency Stability
±50
ppm
Horizontal Sync Input Frequency
14.8
110
kHz
LLC Frequency Range
12.825
170
MHz
I2C PORTS (FAST MODE)3
xCL Frequency4
400
kHz
xCL Minimum Pulse Width High4
t1
0.6
s
xCL Minimum Pulse Width Low4
t2
1.3
s
Hold Time (Start Condition)
t3
0.6
s
Setup Time (Start Condition)
t4
0.6
s
xDA Setup Time4
t5
100
ns
xCL and xDA Rise Times4
t6
300
ns
xCL and xDA Fall Times4
t7
300
ns
Setup Time for Stop Condition
t8
0.6
s
I2C PORTS (NORMAL MODE)3
xCL Frequency4
100
kHz
xCL Minimum Pulse Width High4
t1
4
s
xCL Minimum Pulse Width Low4
t2
4.7
s
Hold Time (Start Condition)
t3
4
s
Setup Time (Start Condition)
t4
4.7
s
xDA Setup Time4
t5
250
ns
xCL and xDA Rise Times4
t6
1000
ns
xCL and xDA Fall Times4
t7
300
ns
Setup Time for Stop Condition
t8
4
s
RESET FEATURE
Reset Pulse Width
5
ms
CLOCK OUTPUTS
LLC Mark-Space Ratio
t9:t10
45:55
55:45
% duty cycle
DATA AND CONTROL OUTPUTS
Data Output Transition Time SDR (SDP)5
t11
Negative clock edge to start of valid data
3.4
ns
t12
End of valid data to negative clock edge
2.4
ns
Data Output Transition Time SDR (CP)6
t13
End of valid data to negative clock edge
2
ns
t14
Negative clock edge to start of valid data
0.5
ns
I2S PORT (MASTER MODE)
SCLK Mark-Space Ratio
t15:t16
45:55
55:45
% duty cycle
LRCLK Data Transition Time
t17
End of valid data to negative SCLK edge
10
ns
t18
Negative SCLK edge to start of valid data
10
ns
I2Sx Data Transition Time7
t19
End of valid data to negative SCLK edge
5
ns
t20
Negative SCLK edge to start of valid data
5
ns
MCLKOUT Frequency
4.096
24.576
MHz
1
The minimum/maximum specifications are guaranteed over the 40°C to +85°C temperature range (TMIN to TMAX).
2
Guaranteed by characterization.
3
Refers to all I2C pins (DDC and control port).
4
The prefix x refers to pin names beginning with S, DDCA_S, and DDCB_S.
5
SDP timing figures were obtained using the default drive strength value (0x15) in User Map Register 0xF4.
6
CP timing figures were obtained using the maximum drive strength value (0x3F) in User Map Register 0xF4.
7
The suffix x refers to pin names ending with 0, 1, 2, and 3.
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