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參數(shù)資料
| 型號(hào)： | ADV7400AKSTZ-80 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 10-Bit Intergrated Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer |
| 中文描述： | 10位集成多格式標(biāo)清/高清視頻解碼器和RGB圖形數(shù)字化儀 |
| 文件頁(yè)數(shù)： | 9/16頁(yè) |
| 文件大?。?/td> | 767K |
| 代理商： | ADV7400AKSTZ-80 |
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ADV7400A
Pin No.
3
Rev. A | Page 9 of 16
Mnemonic
INT
Type
O
Description
Interrupt Pin. This pin can be programmed active low or active high. When SDP/CP
status bits change, this pin triggers an interrupt. The set of events which triggers an
interrupt can be modified via I
2
C registers.
Horizontal Synchronization/Composite Synchronization. HS is a horizontal
synchronization output signal in SDP and CP modes. CS is a digital composite
synchronization signal that can be selected while in CP mode.
Vertical Synchronization. Vertical synchronization output signal in SDP and CP
modes.
Field Synchronization/Data Enable. Field synchronization output signal in all
interlaced video modes. This pin also can be enabled as a data enable signal in CP
mode to allow direct connection to a HDMI/DVI Tx IC.
I
2
C Port Serial Data Input/Output Pin. SDA1 is the data line for the control port and
SDA2 is the data line for the VBI readback port.
I
2
C Port Serial Clock Input (max clock rate of 400 kHz). SCLK1 is the clock line for the
control port, and SCLK2 is the clock line for the VBI data readback port.
This pin selects the I
2
C address for the ADV7400A control and VBI readback ports.
When set to a Logic 0, ALSB sets the address for a write to control port of 0x40 and
the readback address for the VBI port of 0x21. When set to a Logic 1, ALSB sets the
address for a write to the control port of 0x42 and the readback address for the VBI
port of 0x23.
System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required
to reset the ADV7400A circuitry.
Line-locked output clock for the pixel data output by the ADV7400A (the range is
13.5 MHz to 110 MHz for the ADV7400AKSTZ-110; 13.5 MHz to 80 MHz for the
ADV7400AKSTZ-80).
Input pin for 27 MHz crystal, or it can be overdriven by an external 3.3 V 27 MHz clock
oscillator source to clock the ADV7400A.
This pin should be connected to the 27 MHz crystal or left as a no connect if an
external 3.3 V, 27 MHz clock oscillator source is used to clock the ADV7400A. In
crystal mode the crystal must be a fundamental crystal.
The recommend external loop filter must be connected to this ELPF pin.
SFL (Subcarrier Frequency Lock). This pin contains a serial output stream that can be
used to lock the subcarrier frequency when this decoder is connected to any Analog
Devices digital video encoder.
SYNC_OUT is the sliced sync output signal available only in CP mode.
Internal Voltage Reference Output.
Common-Mode Level Pin for the Internal ADCs.
ADC Capacitor Network.
ADC Capacitor Network.
External Bias Setting Pin. Connect the recommended resistor between this pin and
ground.
Can be configured in CP mode to be either a digital HS input signal or a digital CS
input signal, which are used to extract timing in 5-wire or 4-wire RGB mode.
VS Input Signal. Used in CP mode for 5-wire timing mode.
Data Enable Input Signal. Used in 24-bit digital input port mode, for example, 24-bit
RGB data from a DVI Rx IC.
No Connect Pin. This pin can be tied to AGND or AVDD.
Clock Input Signal. Used in 24-bit digital input mode and also in digital CVBS input
mode.
Sync On Green Input Pin. Used in embedded sync mode.
Sync On Luma Input Pin. Used in embedded sync mode.
4
HS/CS
O
99
VS
O
98
FIELD/DE
O
81, 19
SDA1, SDA2
I/O
82, 16
SCLK1, SCLK2
I
80
ALSB
I
78
RESET
I
36
LLC1
O
38
XTAL
I
37
XTAL1
O
46
15
ELPF
SFL/SYNC_OUT
O
O
64
65
61, 62
68, 69
67
REFOUT
CML
CAPY1 to CAPY2
CAPC1 to CAPC2
BIAS
O
O
I
I
O
86
HS_IN/CS_IN
I
85
79
VS_IN
DE_IN
I
I
59
35
NC
DCLK_IN
NC
I
52
77
SOG
SOY
I
I
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADV7400AKSTZ-801 | 10-Bit Intergrated Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer |
| ADV7400ABSTZ-1101 | 10-Bit Intergrated Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer |
| ADV7400AKSTZ-110 | 10-Bit Intergrated Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer |
| ADV7400AKSTZ-1101 | 10-Bit Intergrated Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer |
| ADV7400A | 10-Bit Intergrated Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7400AKSTZ-801 | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit Intergrated Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer |
| ADV7400BST-110 | 制造商:Analog Devices 功能描述: |
| ADV7400KST-110 | 制造商:Analog Devices 功能描述:Video Decoder 1ADC 10-Bit 100-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:10-BIT 110MHZMULTFMTVIDDECOD I.C. - Bulk |
| ADV7400KST-140 | 制造商:AD 制造商全稱:Analog Devices 功能描述:ADV7402/ADV7400 Multiformat Video Decoders for Advanced TV |
| ADV7400KST-80 | 制造商:Analog Devices 功能描述:Video Decoder 1ADC 10-Bit 100-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:MULTI-FORMAT SDTV / HDTV VIDEO DECODER WITH RGB GRAPHICS DI - Bulk |
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