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參數資料
| 型號： | ADV7400AKSTZ-80 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 10-Bit Intergrated Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer |
| 中文描述： | 10位集成多格式標清/高清視頻解碼器和RGB圖形數字化儀 |
| 文件頁數： | 5/16頁 |
| 文件大小： | 767K |
| 代理商： | ADV7400AKSTZ-80 |
ADV7400A
TIMING CHARACTERISTICS
A
VDD
= 3.15 V to 3.45 V, D
VDD
= 1.65 V to 2.0 V, D
VDDIO
= 3.0 V to 3.6 V, P
VDD
= 1.65 V to 2.0 V, operating temperature range, unless
otherwise noted.
Table 3. Timing Characteristics
1, ,
Parameter
Symbol Test Conditions
SYSTEM CLOCK AND CRYSTAL
Crystal Nominal Frequency
Crystal Frequency Stability
Horizontal Sync Input Frequency
LLC1 Frequency Range
4
I
2
C PORT
SCLK Frequency
SCLK Min Pulse Width High
t
1
SCLK Min Pulse Width Low
t
2
Hold Time (Start Condition)
t
3
Setup Time (Start Condition)
t
4
SDA Setup Time
t
5
SCLK and SDA Rise Time
t
6
SCLK and SDA Fall Time
t
7
Setup Time for Stop Condition
t
8
RESET FEATURE
Reset Pulse Width
CLOCK OUTPUTS
LLC1 Mark Space Ratio
t
9
:t
10
Rev. A | Page 5 of 16
2 3
Min
14.8
12.825
0.6
1.3
0.6
0.6
100
5
45:55
Typ
27.0
0.6
Max
±50
110
110
400
300
300
55:45 % duty
Unit
MHz
ppm
kHz
MHz
kHz
μs
μs
μs
μs
ns
ns
ns
μs
ms
cycle
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DATA and CONTROL OUTPUTS
Data Output Transition Time (SDP)
Data Output Transition Time (SDP)
Data Output Transition Time (CP)
Data Output Transition Time (CP)
Data Output Transition Time DDR (CP)
5
t
15
Data Output Transition Time DDR (CP)
5
t
16
Data Output Transition Time DDR (CP)
5
t
17
Data Output Transition Time DDR (CP)
5
t
18
DATA and CONTROL INPUTS
Input Setup Time
Input Hold Time
1
The min/max specifications are guaranteed over this range.
2
Temperature range T
MIN
to T
MAX
:
40°C to +85°C.
3
Guaranteed by characterization.
4
Maximum LLC1 frequency is 80 MHz for the ADV7400AKSTZ-80.
5
DDR timing specifications depend on LLC1 output pixel clock; T
LCC1
/4 = 9.25 ns at LLC1 = 27 MHz.
t
11
t
12
t
13
t
14
Negative clock edge to start of valid data
End of valid data to negative clock edge
End of valid data to negative clock edge
Negative clock edge to start of valid edge
Positive clock edge to end of valid data
Start of valid data to positive clock edge
Negative clock edge to end of valid data
Start of valid data to negative clock edge
HS_IN, VS_IN
HS_IN, VS_IN
DE_IN, data inputs
3.4
2.4
1.1
2.2
2.7 + T
LLC1
/4
1.3 + T
LLC1
/4
2.1 + T
LLC1
/4
0.9 + T
LLC1
/4
9
2.2
7
1
t
19
t
20
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| ADV7400AKSTZ-110 | 10-Bit Intergrated Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ADV7400AKSTZ-801 | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit Intergrated Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer |
| ADV7400BST-110 | 制造商:Analog Devices 功能描述: |
| ADV7400KST-110 | 制造商:Analog Devices 功能描述:Video Decoder 1ADC 10-Bit 100-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:10-BIT 110MHZMULTFMTVIDDECOD I.C. - Bulk |
| ADV7400KST-140 | 制造商:AD 制造商全稱:Analog Devices 功能描述:ADV7402/ADV7400 Multiformat Video Decoders for Advanced TV |
| ADV7400KST-80 | 制造商:Analog Devices 功能描述:Video Decoder 1ADC 10-Bit 100-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:MULTI-FORMAT SDTV / HDTV VIDEO DECODER WITH RGB GRAPHICS DI - Bulk |
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