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參數資料
| 型號： | ADV7393-DBRDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 45/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADV7393 |
| 產品變化通告： | ADV734x, ADV739x Feature Improvement |
| 設計資源： | Reconstruction Video Filter Using ADA4430-1 Amplifier After ADV7393 Video Encoder (CN0101) |
| 標準包裝： | 1 |
| 系列： | Advantiv® |
| 主要目的： | 視頻，視頻編碼器 |
| 已用 IC / 零件： | ADV7393 |
| 已供物品： | 板 |
| 相關產品： | ADV7393BCPZ-ND - IC DAC VIDEO HDTV 10BIT 40LFCSP ADV7393BCPZ-REEL-ND - IC DAC ENCODER VID HDTV 40-LFCSP |
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Data Sheet
ADV7390/ADV7391/ADV7392/ADV7393
Rev. G | Page 41 of 108
SR7 to
Reset
SR0
Register
Bit Description
7
6
5
4
3
2
1
0
Register Setting
Value
0x8B
SD Timing Register 1
Note: Applicable in
master modes only,
that is, Subaddress
0x8A, Bit 0 = 1.
SD HSYNC width
0
ta = one clock cycle.
0x00
0
1
ta = four clock cycles.
1
0
ta = 16 clock cycles.
1
ta = 128 clock cycles.
SD HSYNC to VSYNC delay
0
tb = 0 clock cycles.
0
1
tb = four clock cycles.
1
0
tb = eight clock cycles.
1
tb = 18 clock cycles.
SD HSYNC to VSYNC rising
edge delay (Mode 1 only)
0
tc = tb.
1
tc = tb + 32 s.
SD VSYNC width (Mode 2 only)
0
One clock cycle.
0
1
Four clock cycles.
1
0
16 clock cycles.
1
128 clock cycles.
SD HSYNC to pixel data adjust
0
0 clock cycles.
0
1
One clock cycle.
1
0
Two clock cycles.
1
Three clock cycles.
0x8C
Subcarrier Frequency Bits[7:0]
x
Subcarrier Frequency
Bits[7:0].
0x1F
0x8D
Subcarrier Frequency Bits[15:8]
x
Subcarrier Frequency
Bits[15:8].
0x7C
0x8E
Subcarrier Frequency Bits[23:16]
x
Subcarrier Frequency
Bits[23:16].
0xF0
0x8F
Subcarrier Frequency Bits[31:24]
x
Subcarrier Frequency
Bits[31:24].
0x21
0x90
SD FSC Phase
Subcarrier Phase Bits[9:2]
x
Subcarrier Phase Bits[9:2].
0x00
0x91
SD Closed Captioning
Extended data on even fields
x
Extended Data Bits[7:0].
0x00
0x92
SD Closed Captioning
Extended data on even fields
x
Extended Data Bits[15:8].
0x00
0x93
SD Closed Captioning
Data on odd fields
x
Data Bits[7:0].
0x00
0x94
SD Closed Captioning
Data on odd fields
x
Data Bits[15:8].
0x00
0x95
SD Pedestal Register 0
Pedestal on odd fields
17
16
15
14
13
12
11
10
Setting any of these bits
to 1 disables the
pedestal on the line
number indicated by
the bit settings.
0x00
0x96
SD Pedestal Register 1
Pedestal on odd fields
25
24
23
22
21
20
19
18
0x00
0x97
SD Pedestal Register 2
Pedestal on even fields
17
16
15
14
13
12
11
10
0x00
0x98
SD Pedestal Register 3
Pedestal on even fields
25
24
23
22
21
20
19
18
0x00
1
x = Logic 0 or Logic 1.
2
X = don’t care.
3
SD subcarrier frequency registers default to NTSC subcarrier frequency values.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ADV7393EBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| ADV7393WBCPZ | 制造商:Analog Devices 功能描述:LOW POWER, CHIP SCALE 10-BIT SD/HD VIDEO ENCODER - Trays |
| ADV7393WBCPZ-REEL | 制造商:Analog Devices 功能描述:LOW POWER, CHIP SCALE 10-BIT SD/HD VIDEO ENCODER - Tape and Reel |
| ADV73946603 | 制造商:LG Corporation 功能描述:Frame Assembly |
| ADV73946604 | 制造商:LG Corporation 功能描述:Frame Assembly |
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