- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374048 > ADV7391BCPZ (ANALOG DEVICES INC) Low Power, Chip Scale 10-Bit SD/HD Video Encoder PDF資料下載
參數(shù)資料
| 型號： | ADV7391BCPZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| 中文描述： | COLOR SIGNAL ENCODER, QCC32 |
| 封裝： | 5 X 5 MM, ROHS COMPLIANT, MO-220VHHD-2, LFSCP-32 |
| 文件頁數(shù)： | 30/96頁 |
| 文件大?。?/td> | 1209K |
| 代理商： | ADV7391BCPZ |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁當(dāng)前第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁
ADV7390/ADV7391/ADV7392/ADV7393
Table 18. Register 0x34 to Register 0x38
SR7 to
SR0
Register
0x34
ED/HD Mode
Register 5
Rev. 0 | Page 30 of 96
Bit Description
ED/HD Timing Reset.
Bit Number
5
4
0
1
0
Register Setting
Internal ED/HD timing counters enabled
Resets the internal ED/HD timing counters
HSYNC output control (refer to
Table 50
)
Reset
Value
0x48
7
6
3
1
2
0
1
1
0
1
0
0
1
ED/HD HSYNC Control.
1
ED/HD VSYNC Control.
1
VSYNC output control (refer to
Table 51
)
Reserved.
ED Macrovision Enable.
2
ED Macrovision disabled
ED Macrovision enabled
0 must be written to this bit
Reserved.
0
1
0
1
x
x
x
0
1
0
1
x
x
x
0
1
x
x
x
0
1
x
x
x
0
1
x
x
x
0
1
x
x
x
0
x
x
x
0
x
x
x
0 = Field input
1 = VSYNC input
Update field/line counter
Field/line counter free running
Disabled
Enabled
DAC 2 = Pb, DAC 3 = Pr
DAC 2 = Pr, DAC 3 = Pb
Gamma Correction Curve A
Gamma Correction Curve B
Disabled
Enabled
Mode A
Mode B
Disabled
Enabled
Y level value
Cr level value
Cb level value
ED/HD VSYNC Input/Field
Input.
ED/HD Horizontal/Vertical
Counter Mode.
3
Reserved.
Reserved.
ED/HD Sync on PrPb.
0x00
ED/HD Color DAC Swap.
ED/HD Gamma Correction
Curve Select.
ED/HD Gamma
Correction Enable.
ED/HD Adaptive
Filter Mode.
0x35
ED/HD Mode
Register 6
ED/HD Adaptive
Filter Enable.
0x36
0x37
0x38
1
Used in conjunction with ED/HD sync output enable in Subaddress 0x02, Bit 7 = 1.
2
Applies to the ADV7390 and ADV7392 only.
3
When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the
horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.
4
For use with ED/HD internal test patterns only (Subaddress 0x31, Bit 2 = 1).
ED/HD Y Level
4
ED/HD Cr Level
4
ED/HD Cb Level
4
ED/HD Test Pattern Y Level.
ED/HD Test Pattern Cr Level.
ED/HD Test Pattern Cb Level.
0xA0
0x80
0x80
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADV7391BCPZ-REEL | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| ADV7391EBZ | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| ADV7392 | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| ADV7392BCPZ | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| ADV7392BCPZ-REEL | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7391BCPZ-REEL | 功能描述:IC VIDEO ENCODER SD/HD 32-LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7391EBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| ADV7391WBCPZ | 制造商:Analog Devices 功能描述: |
| ADV7391WBCPZ-RL | 制造商:Analog Devices 功能描述: |
| ADV7392 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。