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參數(shù)資料
| 型號： | ADV7390EBZ |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| 中文描述： | 低功耗，芯片尺寸10位標清/高清視頻編碼器 |
| 文件頁數(shù)： | 58/96頁 |
| 文件大?。?/td> | 1209K |
| 代理商： | ADV7390EBZ |
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ADV7390/ADV7391/ADV7392/ADV7393
Coring Gain Border—Subaddress 0xA3, Bits[3:0]
These four bits are assigned to the gain factor applied to border
areas. In DNR mode, the range of gain values is 0 to 1 in
increments of 1/8. This factor is applied to the DNR filter
output that lies below the set threshold range. The result is then
subtracted from the original signal.
In DNR sharpness mode, the range of gain values is 0 to 0.5 in
increments of 1/16. This factor is applied to the DNR filter
output that lies above the threshold range. The result is added to
the original signal.
Coring Gain Data—Subaddress 0xA3, Bits[7:4]
These four bits are assigned to the gain factor applied to the luma
data inside the MPEG pixel block. In DNR mode, the range of
gain values is 0 to 1 in increments of 1/8. This factor is applied
to the DNR filter output that lies below the set threshold range.
The result is then subtracted from the original signal.
In DNR sharpness mode, the range of gain values is 0 to 0.5 in
increments of 1/16. This factor is applied to the DNR filter
output that lies above the threshold range. The result is added to
the original signal.
Rev. 0 | Page 58 of 96
O X X X X X X O O X X X X X X O
O X X X X X X O O X X X X X X O
O X X X X X X O O X X X X X X O
DNR27 TO DNR24 = 0x01
OFFSET CAUSED
BY VARIATIONS IN
APPLY BORDER
CORING GAIN
APPLY DATA
CORING GAIN
0
Figure 80. SD DNR Offset Control
DNR Threshold—Subaddress 0xA4, Bits[5:0]
These six bits are used to define the threshold value in the range
of 0 to 63. The range is an absolute value.
Border Area—Subaddress 0xA4, Bit 6
When this bit is set to Logic 1, the block transition area can be
defined to consist of four pixels. If this bit is set to Logic 0, the
border transition area consists of two pixels, where one pixel
refers to two clock cycles at 27 MHz.
720 × 485 PIXELS
(NTSC)
8 × 8 PIXEL BLOCK
2-PIXEL
BORDER
DATA
8 × 8 PIXEL BLOCK
0
Figure 81. SD DNR Border Area
Block Size—Subaddress 0xA4, Bit 7
This bit is used to select the size of the data blocks to be
processed. Setting the block size control function to Logic 1
defines a 16 pixel × 16 pixel data block, and Logic 0 defines an
8 pixel × 8 pixel data block, where one pixel refers to two clock
cycles at 27 MHz.
DNR Input Select—Subaddress 0xA5, Bits[2:0]
These three bits are assigned to select the filter that is applied to
the incoming Y data. The signal that lies in the pass band of the
selected filter is the signal processed by DNR. Figure 82 shows
the filter responses selectable with this control.
FILTER C
FILTER B
FILTER A
FILTER D
FREQUENCY (MHz)
0
0.2
0.4
0.6
M
0.8
1.0
0
1
2
3
4
5
6
0
Figure 82. SD DNR Input Select
DNR Mode—Subaddress 0xA5, Bit 4
This bit controls the DNR mode selected. Logic 0 selects DNR
mode; Logic 1 selects DNR sharpness mode.
DNR works on the principle of defining low amplitude, high
frequency signals as probable noise and subtracting this noise
from the original signal.
In DNR mode, it is possible to subtract a fraction of the signal
that lies below the set threshold, assumed to be noise, from the
original signal. The threshold is set in DNR Register 1.
When DNR sharpness mode is enabled, it is possible to add a
fraction of the signal that lies above the set threshold to the
original signal because this data is assumed to be valid data and
not noise. The overall effect is that the signal is boosted (similar
to using the extended SSAF filter).
Block Offset Control—Subaddress 0xA5, Bits[7:4]
Four bits are assigned to this control that allows a shift in the
data block of 15 pixels maximum. The coring gain positions are
fixed. The block offset shifts the data in steps of one pixel such
that the border coring gain factors can be applied at the same
position regardless of variations in input timing of the data.
相關PDF資料 |
PDF描述 |
|---|---|
| ADV7391 | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| ADV7391BCPZ | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| ADV7391BCPZ-REEL | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| ADV7391EBZ | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| ADV7392 | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7390WBCPZ | 功能描述:IC VIDEO ENCODER 10BIT 32LFCSP 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:視頻編碼器 應用:DVD，游戲控制臺，媒體播放器 電壓 - 電源，模擬:2.6 V ~ 3.46 V 電壓 - 電源，數(shù)字:1.71 V ~ 1.89 V 安裝類型:表面貼裝 封裝/外殼:32-WFQFN 裸露焊盤，CSP 供應商器件封裝:32-LFCSP-WQ（5x5） 標準包裝:1 |
| ADV7390WBCPZ-RL | 功能描述:Video Encoder IC DVD, Game Consoles, Media Players 32-LFCSP-WQ (5x5) 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):有效 類型:視頻編碼器 應用:DVD，游戲控制臺，媒體播放器 電壓 - 電源，模擬:2.6 V ~ 3.46 V 電壓 - 電源，數(shù)字:1.71 V ~ 1.89 V 安裝類型:表面貼裝 封裝/外殼:32-WFQFN 裸露焊盤，CSP 供應商器件封裝:32-LFCSP-WQ（5x5） 標準包裝:5,000 |
| ADV7391 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| ADV7391BCBZ-A-RL | 功能描述:視頻 IC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| ADV7391BCPZ | 功能描述:IC ENCODER VIDEO W/DAC 32LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
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