- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374048 > ADV7390EBZ (Analog Devices, Inc.) Low Power, Chip Scale 10-Bit SD/HD Video Encoder PDF資料下載
參數(shù)資料
| 型號(hào)： | ADV7390EBZ |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| 中文描述： | 低功耗，芯片尺寸10位標(biāo)清/高清視頻編碼器 |
| 文件頁(yè)數(shù)： | 43/96頁(yè) |
| 文件大小： | 1209K |
| 代理商： | ADV7390EBZ |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)當(dāng)前第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)
ADV7390/ADV7391/ADV7392/ADV7393
ENHANCED DEFINITION/HIGH DEFINITION
Subaddress 0x01, Bits[6:4] = 001 or 010
ED or HD YCrCb data can be input in a 4:2:2 format over an
8-/10-bit DDR bus or a 16-bit SDR bus.
The clock signal must be provided on the CLKIN pin. If
required, external synchronization signals can be provided on
the HSYNC and VSYNC pins. Embedded EAV/SAV timing
codes are also supported.
16-Bit 4:2:2 YCrCb Mode (SDR)
In 16-bit 4:2:2 YCrCb input mode, the Y pixel data is input on
Pin P15 to Pin P8, with P8 being the LSB.
The CrCb pixel data is input on Pin P7 to Pin P0, with P0
being the LSB.
8-/10-Bit 4:2:2 YCrCb Mode (DDR)
In 8-/10-bit DDR 4:2:2 YCrCb input mode, the Y pixel data is
input on Pin P15 to Pin P8/P6 upon either the rising or falling
edge of CLKIN. P8/P6 is the LSB.
The CrCb pixel data is also input on Pin P15 to Pin P8/P6
upon the opposite edge of CLKIN. P8/P6 is the LSB.
10-bit mode is enabled using Subaddress 0x33, Bit 2. Whether
the Y data is clocked in upon the rising or falling edge of CLKIN
is determined by Subaddress 0x01, Bits[2:1] (see Figure 55 and
Figure 56).
Rev. 0 | Page 43 of 96
3FF
00
00
X
Y
Y0
Y1
Cr0
CLKIN
NOTES
1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 00 IN THIS CASE.
2. 10-BIT MODE IS ENABLED USING SUBADDRESS 0x33, BIT 2.
P[15:8]/
P]15:6]
Cb0
0
Figure 55. ED/HD-DDR Input Sequence (EAV/SAV)—Option A
3FF
00
00
XY
Cb0
Cr0
Y1
CLKIN
P[15:8]/
P[15:P6]
Y0
NOTES
1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 11 IN THIS CASE.
2. 10-BIT MODE IS ENABLED USING SUBADDRESS 0x33, BIT 2.
Figure 56. ED/HD-DDR Input Sequence (EAV/SAV)—Option B
0
M
PEG2
DECODER
CLKIN
P[7:0]
P[15:8]
INTERLACED TO
PROGRESSIVE
YCrCb
ADV7392/
ADV7393
VSYNC
HSYNC
8
CrCb
8
Y
2
0
Figure 57. ED/HD-SDR Example Application
MPEG2
DECODER
CLKIN
P[15:8]/P[15:6]
INTERLACED TO
PROGRESSIVE
YCrCb
ADV7392/
ADV7393
VSYNC
HSYNC
8/10
2
YCrCb
0
Figure 58. ED/HD-DDR Example Application
ENHANCED DEFINITION (AT 54 MHz)
Subaddress 0x01, Bits[6:4] = 111
ED YCrCb data can be input in an interleaved 4:2:2 format on
an 8-/10-bit bus at a rate of 54 MHz.
A 54 MHz clock signal must be provided on the CLKIN pin.
Embedded EAV/SAV timing codes are supported. External
synchronization signals are not supported in this mode.
The interleaved pixel data is input on Pin P15 to Pin P8/P6,
with P8/P6 being the LSB.
10-bit mode is enabled using Subaddress 0x33, Bit 2.
3FF
00
00
XY
Cb0
Y0
Y1
Cr0
CLKIN
P[15:8]/P[15:6]
NOTES
1. 10-BIT MODE IS ENABLED USING SUBADDRESS 0x33, BIT 2.
0
Figure 59. ED (At 54 MHz) Input Sequence (EAV/SAV)
MPEG2
DECODER
CLKIN
P[15:8]/P[15:6]
54MHz
ADV7392/
ADV7393
VSYNC,
HSYNC
YCrCb
8/10
YCrCb
2
INTERLACED TO
PROGRESSIVE
0
Figure 60. ED (At 54 MHz) Example Application
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADV7391 | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| ADV7391BCPZ | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| ADV7391BCPZ-REEL | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| ADV7391EBZ | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| ADV7392 | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7390WBCPZ | 功能描述:IC VIDEO ENCODER 10BIT 32LFCSP 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:視頻編碼器 應(yīng)用:DVD，游戲控制臺(tái)，媒體播放器 電壓 - 電源，模擬:2.6 V ~ 3.46 V 電壓 - 電源，數(shù)字:1.71 V ~ 1.89 V 安裝類型:表面貼裝 封裝/外殼:32-WFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:32-LFCSP-WQ（5x5） 標(biāo)準(zhǔn)包裝:1 |
| ADV7390WBCPZ-RL | 功能描述:Video Encoder IC DVD, Game Consoles, Media Players 32-LFCSP-WQ (5x5) 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):有效 類型:視頻編碼器 應(yīng)用:DVD，游戲控制臺(tái)，媒體播放器 電壓 - 電源，模擬:2.6 V ~ 3.46 V 電壓 - 電源，數(shù)字:1.71 V ~ 1.89 V 安裝類型:表面貼裝 封裝/外殼:32-WFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:32-LFCSP-WQ（5x5） 標(biāo)準(zhǔn)包裝:5,000 |
| ADV7391 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| ADV7391BCBZ-A-RL | 功能描述:視頻 IC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| ADV7391BCPZ | 功能描述:IC ENCODER VIDEO W/DAC 32LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。