- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374047 > ADV7342 (Analog Devices, Inc.) Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs PDF資料下載
參數(shù)資料
| 型號(hào)： | ADV7342 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs |
| 中文描述： | 六多格式視頻編碼器，11位，297兆赫數(shù)模轉(zhuǎn)換器 |
| 文件頁數(shù)： | 26/88頁 |
| 文件大小： | 1053K |
| 代理商： | ADV7342 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁當(dāng)前第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁
ADV7342/ADV7343
Figure 49 shows an example of data transfer for a write sequence and the start and stop conditions. Figure 50 shows bus write and read
sequences.
Rev. 0 | Page 26 of 88
SDA
SCL
START ADDR R/W ACK
SUBADDRESS ACK
Figure 49. I
2
C Data Transfer
DATA
ACK
STOP
1–7
8
9
S
1–7
1–7
P
8
9
8
9
0
WRITE
SEQUENCE
READ
SEQUENCE
S
SLAVE ADDR
A(S)
SUBADDR
A(S)
DATA
DATA
A(S)
P
S
SLAVE ADDR
A(S)
SUBADDR
A(S) S
SLAVE ADDR
A(S)
DATA
DATA
A(M)
A(M) P
S = START BIT
P = STOP BIT
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
A(S) = NO-ACKNOWLEDGE BY SLAVE
A(M) = NO-ACKNOWLEDGE BY MASTER
LSB = 0
LSB = 1
A(S)
0
Figure 50. I
2
C Read and Write Sequence
SPI OPERATION
The ADV7342/ADV7343 support a 4-wire serial (SPI-compatible)
bus connecting multiple peripherals. Two inputs, master out
slave in (MOSI) and serial clock (SCLK), and one output,
master in slave out (MISO), carry information between a
master SPI peripheral on the bus and the ADV7342/ADV7343.
Each slave device on the bus has a slave select pin that is
connected to the master SPI peripheral by a unique slave select
line. As such, slave device addressing is not required.
To invoke SPI operation, a master SPI peripheral (for example,
a microprocessor) should issue three low pulses on the ADV7342/
ADV7343 ALSB/SPI_SS pin. When the encoder detects the
third rising edge on the ALSB/SPI_SS pin, it automatically
switches to SPI communication mode. The ADV7342/ADV7343
remain in SPI communication mode until a reset or power-
down occurs.
To control the ADV7342/ADV7343, use the following protocol
for both read and write transactions. First, the master initiates a
data transfer by driving and holding the ADV7342/ADV7343
ALSB/SPI_SS pin low. On the first SCLK rising edge after
ALSB/SPI_SS has been driven low, the write command, defined
as 0xD4, is written to the ADV7342/ADV7343 over the MOSI
line. The second byte written to the MOSI line is interpreted as
the starting subaddress. Data on the MOSI line is written MSB
first and clocked on the rising edge of SCLK.
There is a subaddress auto-increment facility. This allows data
to be written to or read from registers in ascending subaddress
sequence starting at any valid subaddress. The user can also
access any unique subaddress register on a one-by-one basis.
In a write data transfer, 8-bit data bytes are written to the
ADV7342/ADV7343, MSB first, on the MOSI line immediately
after the starting subaddress. The data bytes are clocked into the
ADV7342/ADV7343 on the rising edge of SCLK. When all data
bytes have been written, the master completes the transfer by
driving and holding the ALSB/SPI_SS pin high.
In a read data transfer, after the subaddress has been clocked in
on the MOSI line, the ALSB/SPI_SS pin is driven and held high
for at least one clock cycle. Then, the ALSB/SPI_SS pin is driven
and held low again. On the first SCLK rising edge after
ALSB/SPI_SS has been driven low, the read command, defined
as 0xD5, is written, MSB first, to the ADV7342/ADV7343 over
the MOSI line. Subsequently, 8-bit data bytes are read from the
ADV7342/ADV7343, MSB first, on the MISO line. The data
bytes are clocked out of the ADV7342/ADV7343 on the falling
edge of SCLK. When all data bytes have been read, the master
completes the transfer by driving and holding the ALSB/SPI_SS
pin high.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADV7342BSTZ | Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs |
| ADV7343 | Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs |
| ADV7344 | Multiformat Video Encoder Six 14-Bit Noise Shaped Video DACs |
| ADV7344BSTZ | Multiformat Video Encoder Six 14-Bit Noise Shaped Video DACs |
| ADV7390 | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7342BSTZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs |
| ADV7343 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs |
| ADV7343BSTZ | 功能描述:IC ENCODER VIDEO W/DAC 64-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7343WBSTZ | 功能描述:IC ENCODER VID 12BIT DAC 64LQFP 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:視頻編碼器 應(yīng)用:DVD，Blu-Ray 電壓 - 電源，模擬:2.6 V ~ 3.46 V 電壓 - 電源，數(shù)字:1.71 V ~ 1.89 V 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商器件封裝:64-LQFP（10x10） 標(biāo)準(zhǔn)包裝:1 |
| ADV7343WBSTZ-RL | 功能描述:Video Encoder IC DVD, Blu-Ray 64-LQFP (10x10) 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):有效 類型:視頻編碼器 應(yīng)用:DVD，Blu-Ray 電壓 - 電源，模擬:2.6 V ~ 3.46 V 電壓 - 電源，數(shù)字:1.71 V ~ 1.89 V 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商器件封裝:64-LQFP（10x10） 標(biāo)準(zhǔn)包裝:1,500 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。